X1
_ASM_INSN_IF_MIPS(0x00000810 | %X1) \
_ASM_INSN_IF_MIPS(0x00200011 | %X1) \
#define OP(X1, X2, X3, X4, rbase) \
X1 ^= t0; \
#define SLP_VEC(X0, X1, X2, X3, X4) { \
cpu_to_le32(X1), \
#define SLP_VEC(X0, X1, X2, X3, X4) {cpu_to_le32(X0), \
cpu_to_le32(X1), \
WL(X1); \
WU(X1);
RL(X1); \
RU(X1); \
WL(X1); \
WU(X1);
RL(X1); \
RU(X1); \
WL(X1); \
WU(X1);
WL(X1); \
WU(X1); \
WL(X1); \
WU(X1);
WL(X1); \
WU(X1); \
I1(X1); I1(X2); I1(Y1); I1(Y2); I1(Z1); I1(Z2);
LOCK(X1); \
RL(X1);
RL(X1); // this one should NOT fail
RL(X1);
RSL(X1);
RSL(X1); // this one should fail
RSL(X1);
RL(X1);
RSL(X1);
WL(X1);
WSL(X1);
RL(X1);
RU(X1);
WL(X1);
WU(X1);
RSL(X1);
RSU(X1);
WSL(X1);
WSU(X1);
RL(X1);
RU(X1);
RL(X1);
RU(X1);
WL(X1);
WU(X1);
RL(X1);
RU(X1);
RL(X1);
RU(X1);
RSL(X1);
RSU(X1);
RSL(X1);
RSU(X1);
WL(X1);
WU(X1);
WL(X1);
WU(X1);
WSL(X1);
WSU(X1);
WSL(X1);
WSU(X1);