XGMAC_DMA_CONTROL
value = readl(priv->base + XGMAC_DMA_CONTROL);
writel(value, priv->base + XGMAC_DMA_CONTROL);
value = readl(ioaddr + XGMAC_DMA_CONTROL);
writel(value, ioaddr + XGMAC_DMA_CONTROL);
u32 value = readl(ioaddr + XGMAC_DMA_CONTROL);
writel(value, ioaddr + XGMAC_DMA_CONTROL);
reg = readl(priv->base + XGMAC_DMA_CONTROL);
writel(reg & ~DMA_CONTROL_ST, priv->base + XGMAC_DMA_CONTROL);
writel(reg | DMA_CONTROL_ST, priv->base + XGMAC_DMA_CONTROL);
writel(DMA_CONTROL_OSF, ioaddr + XGMAC_DMA_CONTROL);
u32 value = readl(ioaddr + XGMAC_DMA_CONTROL);
writel(value, ioaddr + XGMAC_DMA_CONTROL);