XGMAC_DMA_CH_TX_CONTROL
value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)) & XGMAC_EDSE;
value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));