BP_PORT
#define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\
#define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
#define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
#define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
int i, rc, port = BP_PORT(bp);
int port = BP_PORT(bp);
dev_info.port_hw_config[BP_PORT(bp)].
int port = BP_PORT(bp);
return fp->cl_id + BP_PORT(bp) * FP_SB_MAX_E1x;
return fp->cl_id + BP_PORT(fp->bp) * ETH_MAX_RX_CLIENTS_E1H;
u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
return 2 * vn + BP_PORT(bp);
offset += BP_PORT(bp) * mib_size;
BP_PORT(bp)*sizeof(struct lldp_admin_mib))
int port = BP_PORT(bp);
int port = BP_PORT(bp);
int port = BP_PORT(bp);
if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
int port = BP_PORT(bp);
int port = BP_PORT(bp);
if (BP_PORT(bp)) {
BNX2X_PF_Q_NUM(q_num, BP_PORT(bp), vnic);
#ifndef BP_PORT
int port = BP_PORT(bp);
int port = BP_PORT(bp);
u8 port = BP_PORT(bp);
base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp));
BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq);
val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
(MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
(u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
lfa_host_addr[BP_PORT(bp)]));
dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
int cfg_size = 0, idx, port = BP_PORT(bp);
int port = BP_PORT(bp);
int port = BP_PORT(bp);
int port = BP_PORT(bp);
int port = BP_PORT(bp);
int port = BP_PORT(bp);
tmp = BP_PORT(bp);
bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
u8 other_port = !BP_PORT(bp);
SHMEM2_RD(bp, dcbx_en[BP_PORT(bp)])) {
TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
int port = BP_PORT(bp);
TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
offset = SHMEM2_RD(bp, fc_npiv_nvram_tbl_addr[BP_PORT(bp)]);
offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
int port = BP_PORT(bp);
int port = BP_PORT(bp);
int port = BP_PORT(bp);
int port = BP_PORT(bp);
int rc, port = BP_PORT(bp);
int port = BP_PORT(bp);
USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
bp->link_params.port = BP_PORT(bp);
REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8,
int port = BP_PORT(bp);
storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
int port = BP_PORT(bp);
int port = BP_PORT(bp);
storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
int port = BP_PORT(bp);
int port = BP_PORT(bp);
int port = BP_PORT(bp);
int port = BP_PORT(bp);
int port = BP_PORT(bp);
int port = BP_PORT(bp);
opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
int port = BP_PORT(bp);
int port = BP_PORT(bp);
bp->common.shmem2_base, BP_PORT(bp));
REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
(u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
int port = BP_PORT(bp);
REG_WR(bp, (BP_PORT(bp) ?
REG_WR(bp, BP_PORT(bp) ?
REG_WR(bp, BP_PORT(bp) ?
REG_WR(bp, BP_PORT(bp) ?
REG_WR(bp, BP_PORT(bp) ?
REG_WR(bp, BP_PORT(bp) ?
REG_WR(bp, BP_PORT(bp) ?
REG_WR(bp, BP_PORT(bp) ?
REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
int port = BP_PORT(bp);
int rc, i, port = BP_PORT(bp);
int port = BP_PORT(bp);
BP_PORT(bp) * (main_mem_size * 4);
int port = BP_PORT(bp);
int port = BP_PORT(bp);
int port = BP_PORT(bp);
int port = BP_PORT(bp);
int port = BP_PORT(bp);
int port = BP_PORT(bp);
int port = BP_PORT(bp);
offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
u32 reg_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM :
REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM_ENABLE :
cur_query_entry->index = BP_PORT(bp);
cur_query_entry->index = BP_PORT(bp);
cur_query_entry->index = BP_PORT(bp);
int /*abs*/port = BP_PORT(bp);
port = BP_PORT(bp);
int port = BP_PORT(bp);
u32 lpi_reg = BP_PORT(bp) ? MISC_REG_CPMU_LP_SM_ENT_CNT_P1
SHMEM_RD(bp, port_mb[BP_PORT(bp)].stat_nig_timer);
u8 port = BP_PORT(bp);
u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp) * 32 +
u32 port = BP_PORT(bp);
USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), cli));
#define BNX2X_HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
cli + (BP_PORT(bp) * ETH_MAX_RX_CLIENTS_E1H))