WRITE_REG
opti_write_reg(ap, data_rec_timing[clock][pio], WRITE_REG);
iowrite8(data_rec_timing[pci_clock][pio], regio + WRITE_REG);
iowrite8(dma_data_rec_timing[pci_clock][dma], regio + WRITE_REG);
struct WRITE_REG write_reg;
struct WRITE_REG write_reg;
WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR);
do { WRITE_REG(priv, regIMR, IR_RUN); } while (0)
do { WRITE_REG(priv, regIMR, 0); } while (0)
WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
WRITE_REG(priv, f->m.reg_WPTR,
WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR);
WRITE_REG(priv, priv->txd_fifo0.m.reg_WPTR,
WRITE_REG(priv, reg_CFG0, (u32) ((f->da & TX_RX_CFG0_BASE) | fsz_type));
WRITE_REG(priv, reg_CFG1, H32_64(f->da));
WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
WRITE_REG(priv, regRDINTCM0, rdintcm);
WRITE_REG(priv, regTDINTCM0, tdintcm);
WRITE_REG(priv, regINIT_SEMAPHORE, 1);
WRITE_REG(priv, regUNC_MAC2_A, val);
WRITE_REG(priv, regUNC_MAC1_A, val);
WRITE_REG(priv, regUNC_MAC0_A, val);
WRITE_REG(priv, regFRM_LENGTH, 0X3FE0);
WRITE_REG(priv, regPAUSE_QUANT, 0x96);
WRITE_REG(priv, regRX_FIFO_SECTION, 0x800010);
WRITE_REG(priv, regTX_FIFO_SECTION, 0xE00010);
WRITE_REG(priv, regRX_FULLNESS, 0);
WRITE_REG(priv, regTX_FULLNESS, 0);
WRITE_REG(priv, regCTRLST,
WRITE_REG(priv, regVGLB, 0);
WRITE_REG(priv, regMAX_FRAME_A,
WRITE_REG(priv, regRDINTCM0, priv->rdintcm);
WRITE_REG(priv, regRDINTCM2, 0); /*cpu_to_le32(rcm.val)); */
WRITE_REG(priv, regTDINTCM0, priv->tdintcm); /* old val = 0x300064 */
WRITE_REG(priv, regGMAC_RXF_A, GMAC_RX_FILTER_OSEN |
WRITE_REG(priv, regCLKPLL, (val | CLKPLL_SFTRST) + 0x8);
WRITE_REG(priv, regCLKPLL, val & ~CLKPLL_SFTRST);
WRITE_REG(priv, regGMAC_RXF_A, 0);
WRITE_REG(priv, regDIS_PORT, 1);
WRITE_REG(priv, regDIS_QU, 1);
WRITE_REG(priv, regRDINTCM0, 0);
WRITE_REG(priv, regTDINTCM0, 0);
WRITE_REG(priv, regIMR, 0);
WRITE_REG(priv, regRST_QU, 1);
WRITE_REG(priv, regRST_PORT, 1);
WRITE_REG(priv, i, 0);
WRITE_REG(priv, regDIS_PORT, 0);
WRITE_REG(priv, regDIS_QU, 0);
WRITE_REG(priv, regRST_QU, 0);
WRITE_REG(priv, regRST_PORT, 0);
WRITE_REG(priv, data[1], data[2]);
WRITE_REG(priv, reg, val);
WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, ~0);
WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, 0);
WRITE_REG(priv, regRX_MAC_MCST0 + i * 8, 0);
WRITE_REG(priv, regRX_MAC_MCST1 + i * 8, 0);
WRITE_REG(priv, reg, val);
WRITE_REG(priv, regGMAC_RXF_A, rxf_val);
WRITE_REG##size(val, astro_iop_base + addr); \
WRITE_REG##size(val, where); \
WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
WRITE_REG(ioc->imask, ioc->ioc_hpa + IOC_IMASK);
WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG);
WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE);
WRITE_REG(ioc->ibase | 31, ioc->ioc_hpa + IOC_PCOM);
WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa+IOC_IBASE);
WRITE_REG(ioc->imask, ioc->ioc_hpa+IOC_IMASK);
WRITE_REG(tcnfg, ioc->ioc_hpa+IOC_TCNFG);
WRITE_REG(0 | 31, ioc->ioc_hpa+IOC_PCOM);
WRITE_REG(ioc_ctl, sba_dev->sba_hpa+IOC_CTRL);
WRITE_REG(cfg_val, rope_cfg);
WRITE_REG(HF_ENABLE, ioc_hpa + ROPE0_CTL + j);
WRITE_REG( SBA_IOVA(ioc, iovp, 0, 0), ioc->ioc_hpa+IOC_PCOM);