drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

228

WREG32_SOC15_IP(GC, reg, mqd_hqd[reg - hqd_base]);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

214

WREG32_SOC15_IP(GC, reg, mqd_hqd[reg - hqd_base]);

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c

1051

WREG32_SOC15_IP(GC, reg, tmp) :

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c

1052

WREG32_SOC15_IP(MMHUB, reg, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5451

WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9079

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9085

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9132

WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9138

WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9247

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9261

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9293

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9307

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9338

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9436

WREG32_SOC15_IP(GC, target, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9446

WREG32_SOC15_IP(GC, target, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2277

WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6423

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6431

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6480

WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6488

WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6605

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6619

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6651

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6665

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6696

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6805

WREG32_SOC15_IP(GC, target, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6815

WREG32_SOC15_IP(GC, target, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

1906

WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4746

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4754

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4797

WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4805

WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4922

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4936

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4968

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4982

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

5013

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

6053

WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

6059

WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

6115

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

6151

WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);

drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c

62

WREG32_SOC15_IP(MMHUB, reg, tmp);

drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c

90

WREG32_SOC15_IP(MMHUB, reg, tmp);

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

502

WREG32_SOC15_IP(MMHUB, reg, tmp);

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

530

WREG32_SOC15_IP(MMHUB, reg, tmp);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

397

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev,

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

400

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev,

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

570

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

573

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

634

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

636

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

638

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

712

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

716

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), lower_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

717

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), upper_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

718

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

719

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

721

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

722

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

723

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

724

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

728

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

730

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

737

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

741

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

743

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

748

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

750

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

757

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

777

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

778

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET),

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

788

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

822

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

830

WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

420

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

423

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

478

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

480

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

482

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

550

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

561

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

565

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), lower_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

566

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), upper_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

567

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

568

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

570

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

571

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

572

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

573

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

578

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

580

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

587

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

591

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

593

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

598

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

599

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

605

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

622

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

623

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

634

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

650

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

659

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

669

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

677

WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

233

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev,

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

236

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev,

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

403

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

406

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

469

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), f32_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

495

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

507

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

511

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), lower_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

512

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), upper_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

513

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

514

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

516

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

517

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

518

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

519

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

523

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO),

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

525

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI),

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

529

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI),

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

531

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO),

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

538

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

539

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

545

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

548

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

549

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

562

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

563

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

574

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

581

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL), temp);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

587

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

596

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

603

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), temp);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

608

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

616

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

771

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE), tmp);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

775

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), tmp);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

777

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_PREEMPT), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

233

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev,

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

237

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev,

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

405

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

408

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

460

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL), mcu_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

497

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

501

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), lower_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

502

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), upper_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

503

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

504

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

506

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

507

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

508

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

509

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

513

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO),

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

515

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI),

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

519

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI),

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

521

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO),

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

532

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

533

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

539

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

542

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

543

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

556

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

557

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

568

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

575

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL), temp);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

581

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

589

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

596

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL), temp);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

601

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

609

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

719

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_CNTL), tmp);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

721

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_BASE_LO),

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

723

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_BASE_HI),

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

728

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_OP_CNTL), tmp);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

766

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL), tmp);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

768

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_PREEMPT), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

227

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev,

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

231

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev,

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

375

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

378

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_IB_CNTL), ib_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

411

WREG32_SOC15_IP(GC,

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

442

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_MCU_CNTL), mcu_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

479

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

483

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_RPTR), lower_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

484

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_RPTR_HI), upper_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

485

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

486

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

488

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_RPTR), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

489

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_RPTR_HI), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

490

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_WPTR), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

491

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_WPTR_HI), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

495

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO),

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

497

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI),

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

501

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_RPTR_ADDR_HI),

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

503

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_RPTR_ADDR_LO),

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

514

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_BASE), ring->gpu_addr >> 8);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

515

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

521

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_MINOR_PTR_UPDATE), 1);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

524

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

525

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

538

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_DOORBELL), doorbell);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

539

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_DOORBELL_OFFSET), doorbell_offset);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

550

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_MINOR_PTR_UPDATE), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

557

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_WATCHDOG_CNTL), temp);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

563

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_UTCL1_CNTL), temp);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

571

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_UTCL1_PAGE), temp);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

578

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_MCU_CNTL), temp);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

583

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_CNTL), rb_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

591

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_IB_CNTL), ib_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

708

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_IC_CNTL), tmp);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

710

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_IC_BASE_LO),

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

712

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_IC_BASE_HI),

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

717

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_IC_OP_CNTL), tmp);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

757

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_MCU_CNTL), tmp);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

759

WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_PREEMPT), 0);

drivers/gpu/drm/amd/amdgpu/soc15.c

483

WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, tmp);