WREG32_AND
WREG32_AND(mmDMA0_CORE_PROT + dma_offset,
WREG32_AND(reg, ~0x7FF);
WREG32_AND(mmu_base + MMU_SPI_SEI_CAUSE_OFFSET, ~spi_sei_cause);
WREG32_AND(mmTPC0_EML_CFG_DBG_CNT + tpc_eml_offset,
WREG32_AND(mmSTLB_STLB_FEATURE_EN,
WREG32_AND(reg, ~0x7FF);
WREG32_AND(HDMI0_GC + offset, ~HDMI0_GC_AVMUTE);
WREG32_AND(DC_HPDx_INT_CONTROL(hpd), ~DC_HPDx_INT_POLARITY);
WREG32_AND(DC_HPDx_INT_CONTROL(i), DC_HPDx_INT_POLARITY);
WREG32_AND(HDMI_GC + offset, ~HDMI_GC_AVMUTE);
WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
WREG32_AND(HDMI0_GENERIC_PACKET_CONTROL + offset,
WREG32_AND(HDMI0_GC + offset, ~HDMI0_GC_AVMUTE);
WREG32_AND(HDMI0_INFOFRAME_CONTROL0 + offset,
WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN);
WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN);
WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN);
WREG32_AND(DC_HPDx_INT_CONTROL(i),