drivers/gpu/drm/xe/xe_exec.c

120

u64 addresses[XE_HW_ENGINE_MAX_INSTANCE];

drivers/gpu/drm/xe/xe_exec_queue.c

1092

struct drm_xe_engine_class_instance eci[XE_HW_ENGINE_MAX_INSTANCE];

drivers/gpu/drm/xe/xe_exec_queue.c

1110

if (XE_IOCTL_DBG(xe, !len || len > XE_HW_ENGINE_MAX_INSTANCE))

drivers/gpu/drm/xe/xe_guc_submit.c

1058

u32 wqi[XE_HW_ENGINE_MAX_INSTANCE + (WQ_HEADER_SIZE - 1)];

drivers/gpu/drm/xe/xe_guc_submit.c

845

#define MAX_MLRC_REG_SIZE (13 + XE_HW_ENGINE_MAX_INSTANCE * 2)

drivers/gpu/drm/xe/xe_guc_submit_types.h

53

struct sync_semaphore join[XE_HW_ENGINE_MAX_INSTANCE];

drivers/gpu/drm/xe/xe_guc_submit_types.h

58

(XE_HW_ENGINE_MAX_INSTANCE + 1)];

drivers/gpu/drm/xe/xe_memirq.c

170

XE_HW_ENGINE_MAX_INSTANCE * SZ_4K : SZ_4K;

drivers/gpu/drm/xe/xe_memirq.c

254

memirq_assert(memirq, instance <= XE_HW_ENGINE_MAX_INSTANCE);

drivers/gpu/drm/xe/xe_memirq.c

280

memirq_assert(memirq, instance <= XE_HW_ENGINE_MAX_INSTANCE);

drivers/gpu/drm/xe/xe_sched_job.c

41

XE_HW_ENGINE_MAX_INSTANCE, 0,