drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

460

for (i = 0; i < WM_SET_COUNT; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

684

for (wm_idx = 0; wm_idx < (unsigned int)WM_SET_COUNT; wm_idx++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

346

for (i = 0; i < WM_SET_COUNT; i++)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

392

for (i = 0; i < WM_SET_COUNT; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

624

for (entry_idx = 0; entry_idx < (unsigned int)WM_SET_COUNT; entry_idx++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

432

for (i = 0; i < WM_SET_COUNT; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

627

for (entry_idx = 0; entry_idx < (unsigned int)WM_SET_COUNT; entry_idx++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

503

for (i = 0; i < WM_SET_COUNT; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

755

for (entry_idx = 0; entry_idx < (unsigned int)WM_SET_COUNT; entry_idx++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

394

for (i = 0; i < WM_SET_COUNT; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

582

for (entry_idx = 0; entry_idx < (unsigned int)WM_SET_COUNT; entry_idx++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

360

for (i = 0; i < WM_SET_COUNT; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

562

for (entry_idx = 0; entry_idx < (unsigned int)WM_SET_COUNT; entry_idx++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1000

for (i = 0; i < WM_SET_COUNT; i++)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1200

for (entry_idx = 0; entry_idx < (unsigned int)WM_SET_COUNT; entry_idx++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

889

for (i = 0; i < WM_SET_COUNT; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1340

for (i = 0; i < WM_SET_COUNT; i++)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

647

for (i = 0; i < WM_SET_COUNT; i++) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

726

for (i = 0; i < WM_SET_COUNT; i++) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1393

ranges.num_reader_wm_sets = WM_SET_COUNT;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1394

ranges.num_writer_wm_sets = WM_SET_COUNT;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2191

for (i = 0; i < WM_SET_COUNT; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2198

for (i = 0; i < WM_SET_COUNT; i++) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2209

for (i = 0; i < WM_SET_COUNT; i++) {

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

293

struct nv_wm_range_entry nv_entries[WM_SET_COUNT];

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

294

struct wm_range_table_entry entries[WM_SET_COUNT];