WM_SOCCLK - Linux

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

437

table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

438

table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

439

table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

440

table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

441

table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

476

table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

477

table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

478

table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

479

table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

480

table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

547

table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

548

table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

549

table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

550

table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

551

table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

439

table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

440

table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

441

table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

442

table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

443

table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

405

table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

406

table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

407

table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

408

table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

409

table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

933

table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

934

table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

935

table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

936

table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

937

table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

692

table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

693

table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

694

table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

695

table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

696

table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1340

table->WatermarkRow[WM_SOCCLK][i].WmType = (uint8_t)0;

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1948

table->WatermarkRow[WM_SOCCLK][i].MinClock =

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1950

table->WatermarkRow[WM_SOCCLK][i].MaxClock =

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1952

table->WatermarkRow[WM_SOCCLK][i].MinUclk =

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1954

table->WatermarkRow[WM_SOCCLK][i].MaxUclk =

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

1957

table->WatermarkRow[WM_SOCCLK][i].WmSetting =

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1860

table->WatermarkRow[WM_SOCCLK][i].MinClock =

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1862

table->WatermarkRow[WM_SOCCLK][i].MaxClock =

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1864

table->WatermarkRow[WM_SOCCLK][i].MinUclk =

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1866

table->WatermarkRow[WM_SOCCLK][i].MaxUclk =

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

1869

table->WatermarkRow[WM_SOCCLK][i].WmSetting =

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1627

table->WatermarkRow[WM_SOCCLK][i].MinClock =

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1629

table->WatermarkRow[WM_SOCCLK][i].MaxClock =

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1631

table->WatermarkRow[WM_SOCCLK][i].MinMclk =

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1633

table->WatermarkRow[WM_SOCCLK][i].MaxMclk =

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1636

table->WatermarkRow[WM_SOCCLK][i].WmSetting =

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1084

table->WatermarkRow[WM_SOCCLK][i].MinClock =

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1086

table->WatermarkRow[WM_SOCCLK][i].MaxClock =

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1088

table->WatermarkRow[WM_SOCCLK][i].MinMclk =

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1090

table->WatermarkRow[WM_SOCCLK][i].MaxMclk =

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1093

table->WatermarkRow[WM_SOCCLK][i].WmSetting =

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1095

table->WatermarkRow[WM_SOCCLK][i].WmType =

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

698

table->WatermarkRow[WM_SOCCLK][i].MinClock =

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

700

table->WatermarkRow[WM_SOCCLK][i].MaxClock =

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

702

table->WatermarkRow[WM_SOCCLK][i].MinMclk =

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

704

table->WatermarkRow[WM_SOCCLK][i].MaxMclk =

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

707

table->WatermarkRow[WM_SOCCLK][i].WmSetting =

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

442

table->WatermarkRow[WM_SOCCLK][i].MinClock =

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

444

table->WatermarkRow[WM_SOCCLK][i].MaxClock =

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

446

table->WatermarkRow[WM_SOCCLK][i].MinMclk =

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

448

table->WatermarkRow[WM_SOCCLK][i].MaxMclk =

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

451

table->WatermarkRow[WM_SOCCLK][i].WmSetting =

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

533

table->WatermarkRow[WM_SOCCLK][i].MinClock =

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

535

table->WatermarkRow[WM_SOCCLK][i].MaxClock =

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

537

table->WatermarkRow[WM_SOCCLK][i].MinMclk =

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

539

table->WatermarkRow[WM_SOCCLK][i].MaxMclk =

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

542

table->WatermarkRow[WM_SOCCLK][i].WmSetting =

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

518

table->WatermarkRow[WM_SOCCLK][i].MinClock =

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

520

table->WatermarkRow[WM_SOCCLK][i].MaxClock =

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

522

table->WatermarkRow[WM_SOCCLK][i].MinMclk =

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

524

table->WatermarkRow[WM_SOCCLK][i].MaxMclk =

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

527

table->WatermarkRow[WM_SOCCLK][i].WmSetting =

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

599

table->WatermarkRow[WM_SOCCLK][i].MinClock =

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

601

table->WatermarkRow[WM_SOCCLK][i].MaxClock =

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

603

table->WatermarkRow[WM_SOCCLK][i].MinMclk =

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

605

table->WatermarkRow[WM_SOCCLK][i].MaxMclk =

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

608

table->WatermarkRow[WM_SOCCLK][i].WmSetting =