XE_ENGINE_CLASS_COMPUTE
{ .cls = "ccs", .mask = XE_HW_ENGINE_CCS_MASK, .engine_class = XE_ENGINE_CLASS_COMPUTE },
(q->class == XE_ENGINE_CLASS_RENDER || q->class == XE_ENGINE_CLASS_COMPUTE)) {
case XE_ENGINE_CLASS_COMPUTE:
if (hwe->class == XE_ENGINE_CLASS_COMPUTE)
case XE_ENGINE_CLASS_COMPUTE:
hwe->class == XE_ENGINE_CLASS_COMPUTE)
if (hwe->class != XE_ENGINE_CLASS_COMPUTE)
xe_lrc_dump_default(p, gt, XE_ENGINE_CLASS_COMPUTE);
case XE_ENGINE_CLASS_COMPUTE:
engine_enable_mask(gt, XE_ENGINE_CLASS_COMPUTE));
hwe->class == XE_ENGINE_CLASS_COMPUTE &&
case XE_ENGINE_CLASS_COMPUTE:
[DRM_XE_ENGINE_CLASS_COMPUTE] = XE_ENGINE_CLASS_COMPUTE,
.class = XE_ENGINE_CLASS_COMPUTE,
.class = XE_ENGINE_CLASS_COMPUTE,
.class = XE_ENGINE_CLASS_COMPUTE,
.class = XE_ENGINE_CLASS_COMPUTE,
xe_hw_engine_mask_per_class(hwe->gt, XE_ENGINE_CLASS_COMPUTE);
if (hwe->class == XE_ENGINE_CLASS_COMPUTE && ccs_mask)
if (hwe->class != XE_ENGINE_CLASS_COMPUTE &&
const u8 mocs_read_idx = hwe->class == XE_ENGINE_CLASS_COMPUTE && IS_DGFX(xe) &&
case XE_ENGINE_CLASS_COMPUTE:
u32 ccs_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COMPUTE);
XE_ENGINE_CLASS_COMPUTE);
hwe->class == XE_ENGINE_CLASS_COMPUTE ||
case XE_ENGINE_CLASS_COMPUTE:
hwe->class == XE_ENGINE_CLASS_COMPUTE) {
class == XE_ENGINE_CLASS_COMPUTE))
case XE_ENGINE_CLASS_COMPUTE:
if (stream->hwe->class != XE_ENGINE_CLASS_COMPUTE)
case XE_ENGINE_CLASS_COMPUTE:
[XE_ENGINE_CLASS_COMPUTE] = DRM_XE_ENGINE_CLASS_COMPUTE,
[DRM_XE_ENGINE_CLASS_COMPUTE] = XE_ENGINE_CLASS_COMPUTE,
else if (job->q->class == XE_ENGINE_CLASS_COMPUTE)
else if (job->q->class == XE_ENGINE_CLASS_COMPUTE)
case XE_ENGINE_CLASS_COMPUTE: