drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

398

table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting =

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

400

table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType =

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

403

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

404

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

406

if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

408

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

411

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

414

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

419

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

420

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

423

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

431

table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

432

table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

433

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

434

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

437

table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting =

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

439

table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType =

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

442

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

443

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

445

if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

447

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

450

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

453

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

458

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

459

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

462

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

470

table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

471

table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

472

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

473

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

508

table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting =

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

510

table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType =

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

513

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

514

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

516

if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

518

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

521

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

524

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

529

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

530

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

533

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

541

table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

542

table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

543

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

544

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

400

table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting =

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

402

table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType =

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

405

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

406

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

408

if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

410

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

413

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

416

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

421

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

422

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

425

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

433

table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

434

table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

435

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

436

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

366

table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting =

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

368

table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType =

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

371

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

372

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

374

if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

376

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

379

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

382

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

387

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

388

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

391

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

399

table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

400

table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

401

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

402

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

894

table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting =

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

896

table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType =

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

899

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

900

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

902

if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

904

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

907

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

910

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

915

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

916

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

919

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

927

table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

928

table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

929

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

930

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

652

table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting =

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

654

table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType =

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

657

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

658

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

660

if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

662

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

665

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

668

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

673

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

674

table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

678

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

686

table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

687

table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

688

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

689

table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1337

table->WatermarkRow[WM_DCFCLK][i].WmType = (uint8_t)0;

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1613

table->WatermarkRow[WM_DCFCLK][i].MinClock =

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1615

table->WatermarkRow[WM_DCFCLK][i].MaxClock =

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1617

table->WatermarkRow[WM_DCFCLK][i].MinMclk =

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1619

table->WatermarkRow[WM_DCFCLK][i].MaxMclk =

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

1622

table->WatermarkRow[WM_DCFCLK][i].WmSetting =

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1068

table->WatermarkRow[WM_DCFCLK][i].MinClock =

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1070

table->WatermarkRow[WM_DCFCLK][i].MaxClock =

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1072

table->WatermarkRow[WM_DCFCLK][i].MinMclk =

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1074

table->WatermarkRow[WM_DCFCLK][i].MaxMclk =

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1077

table->WatermarkRow[WM_DCFCLK][i].WmSetting =

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

1079

table->WatermarkRow[WM_DCFCLK][i].WmType =

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

684

table->WatermarkRow[WM_DCFCLK][i].MinClock =

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

686

table->WatermarkRow[WM_DCFCLK][i].MaxClock =

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

688

table->WatermarkRow[WM_DCFCLK][i].MinMclk =

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

690

table->WatermarkRow[WM_DCFCLK][i].MaxMclk =

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

693

table->WatermarkRow[WM_DCFCLK][i].WmSetting =

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

428

table->WatermarkRow[WM_DCFCLK][i].MinClock =

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

430

table->WatermarkRow[WM_DCFCLK][i].MaxClock =

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

432

table->WatermarkRow[WM_DCFCLK][i].MinMclk =

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

434

table->WatermarkRow[WM_DCFCLK][i].MaxMclk =

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

437

table->WatermarkRow[WM_DCFCLK][i].WmSetting =

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

519

table->WatermarkRow[WM_DCFCLK][i].MinClock =

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

521

table->WatermarkRow[WM_DCFCLK][i].MaxClock =

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

523

table->WatermarkRow[WM_DCFCLK][i].MinMclk =

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

525

table->WatermarkRow[WM_DCFCLK][i].MaxMclk =

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

528

table->WatermarkRow[WM_DCFCLK][i].WmSetting =

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

504

table->WatermarkRow[WM_DCFCLK][i].MinClock =

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

506

table->WatermarkRow[WM_DCFCLK][i].MaxClock =

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

508

table->WatermarkRow[WM_DCFCLK][i].MinMclk =

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

510

table->WatermarkRow[WM_DCFCLK][i].MaxMclk =

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

513

table->WatermarkRow[WM_DCFCLK][i].WmSetting =

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

585

table->WatermarkRow[WM_DCFCLK][i].MinClock =

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

587

table->WatermarkRow[WM_DCFCLK][i].MaxClock =

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

589

table->WatermarkRow[WM_DCFCLK][i].MinMclk =

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

591

table->WatermarkRow[WM_DCFCLK][i].MaxMclk =

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

594

table->WatermarkRow[WM_DCFCLK][i].WmSetting =