arch/xtensa/include/asm/cache.h

21

#define ICACHE_WAY_SIZE (XCHAL_ICACHE_SIZE/XCHAL_ICACHE_WAYS)

arch/xtensa/include/asm/cacheasm.h

135

#if XCHAL_ICACHE_SIZE

arch/xtensa/include/asm/cacheasm.h

136

__loop_cache_all \ar \at iii XCHAL_ICACHE_SIZE \

arch/xtensa/include/asm/cacheasm.h

173

#if XCHAL_ICACHE_SIZE

arch/xtensa/include/asm/cacheasm.h

210

#if XCHAL_ICACHE_SIZE

arch/xtensa/include/asm/cacheasm.h

95

#if XCHAL_ICACHE_LINE_LOCKABLE && XCHAL_ICACHE_SIZE

arch/xtensa/include/asm/cacheasm.h

96

__loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE \

arch/xtensa/kernel/setup.c

685

XCHAL_ICACHE_SIZE,