arch/xtensa/include/asm/cache.h

20

#define DCACHE_WAY_SIZE (XCHAL_DCACHE_SIZE/XCHAL_DCACHE_WAYS)

arch/xtensa/include/asm/cacheasm.h

105

#if XCHAL_DCACHE_SIZE

arch/xtensa/include/asm/cacheasm.h

106

__loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE \

arch/xtensa/include/asm/cacheasm.h

115

#if XCHAL_DCACHE_SIZE

arch/xtensa/include/asm/cacheasm.h

116

__loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE \

arch/xtensa/include/asm/cacheasm.h

125

#if XCHAL_DCACHE_SIZE

arch/xtensa/include/asm/cacheasm.h

126

__loop_cache_all \ar \at dii XCHAL_DCACHE_SIZE \

arch/xtensa/include/asm/cacheasm.h

146

#if XCHAL_DCACHE_SIZE

arch/xtensa/include/asm/cacheasm.h

155

#if XCHAL_DCACHE_SIZE

arch/xtensa/include/asm/cacheasm.h

164

#if XCHAL_DCACHE_SIZE

arch/xtensa/include/asm/cacheasm.h

183

#if XCHAL_DCACHE_SIZE

arch/xtensa/include/asm/cacheasm.h

192

#if XCHAL_DCACHE_SIZE

arch/xtensa/include/asm/cacheasm.h

201

#if XCHAL_DCACHE_SIZE

arch/xtensa/include/asm/cacheasm.h

85

#if XCHAL_DCACHE_LINE_LOCKABLE && XCHAL_DCACHE_SIZE

arch/xtensa/include/asm/cacheasm.h

86

__loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE \

arch/xtensa/kernel/setup.c

688

XCHAL_DCACHE_SIZE);