arch/xtensa/include/asm/cache.h

16

#define L1_CACHE_SHIFT XCHAL_DCACHE_LINEWIDTH

arch/xtensa/include/asm/cache.h

22

#define DCACHE_WAY_SHIFT (XCHAL_DCACHE_SETWIDTH + XCHAL_DCACHE_LINEWIDTH)

arch/xtensa/include/asm/cacheasm.h

107

XCHAL_DCACHE_LINEWIDTH 240

arch/xtensa/include/asm/cacheasm.h

117

XCHAL_DCACHE_LINEWIDTH 240

arch/xtensa/include/asm/cacheasm.h

127

XCHAL_DCACHE_LINEWIDTH 1020

arch/xtensa/include/asm/cacheasm.h

147

__loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH

arch/xtensa/include/asm/cacheasm.h

156

__loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH

arch/xtensa/include/asm/cacheasm.h

165

__loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH

arch/xtensa/include/asm/cacheasm.h

184

__loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH 1020

arch/xtensa/include/asm/cacheasm.h

193

__loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH 1020

arch/xtensa/include/asm/cacheasm.h

202

__loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH 1020

arch/xtensa/include/asm/cacheasm.h

87

XCHAL_DCACHE_LINEWIDTH 240