arch/x86/events/amd/core.c

307

static unsigned int event_offsets[X86_PMC_IDX_MAX] __read_mostly;

arch/x86/events/amd/core.c

308

static unsigned int count_offsets[X86_PMC_IDX_MAX] __read_mostly;

arch/x86/events/amd/core.c

437

for_each_set_bit(i, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {

arch/x86/events/amd/core.c

549

for_each_set_bit(i, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {

arch/x86/events/amd/core.c

742

for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {

arch/x86/events/amd/core.c

762

for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {

arch/x86/events/amd/core.c

991

for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {

arch/x86/events/core.c

1026

for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {

arch/x86/events/core.c

1398

DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);

arch/x86/events/core.c

1480

int assign[X86_PMC_IDX_MAX];

arch/x86/events/core.c

1599

for_each_set_bit(idx, cntr_mask, X86_PMC_IDX_MAX) {

arch/x86/events/core.c

1612

for_each_set_bit(idx, fixed_cntr_mask, X86_PMC_IDX_MAX) {

arch/x86/events/core.c

1726

for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {

arch/x86/events/core.c

224

for_each_set_bit(i, (unsigned long *)&cntr_mask, X86_PMC_IDX_MAX) {

arch/x86/events/core.c

229

for_each_set_bit(i, (unsigned long *)&cntr_mask, X86_PMC_IDX_MAX) {

arch/x86/events/core.c

2347

int assign[X86_PMC_IDX_MAX];

arch/x86/events/core.c

240

i = X86_PMC_IDX_MAX;

arch/x86/events/core.c

255

for_each_set_bit(i, (unsigned long *)&cntr_mask, X86_PMC_IDX_MAX) {

arch/x86/events/core.c

2554

if (bitmap_empty(cpuc->dirty, X86_PMC_IDX_MAX))

arch/x86/events/core.c

2557

for_each_set_bit(i, cpuc->dirty, X86_PMC_IDX_MAX) {

arch/x86/events/core.c

2569

bitmap_zero(cpuc->dirty, X86_PMC_IDX_MAX);

arch/x86/events/core.c

280

for_each_set_bit(i, cntr_mask, X86_PMC_IDX_MAX) {

arch/x86/events/core.c

299

for_each_set_bit(i, fixed_cntr_mask, X86_PMC_IDX_MAX) {

arch/x86/events/core.c

710

for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {

arch/x86/events/core.c

767

for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {

arch/x86/events/core.c

905

for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {

arch/x86/events/intel/core.c

3347

for_each_set_bit(idx, (unsigned long *)&event->attr.config2, X86_PMC_IDX_MAX) {

arch/x86/events/intel/core.c

3487

for_each_set_bit(bit, (unsigned long *)&guest_pebs_idxs, X86_PMC_IDX_MAX) {

arch/x86/events/intel/core.c

3609

for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {

arch/x86/events/intel/core.c

4179

for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) {

arch/x86/events/intel/core.c

4231

bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX);

arch/x86/events/intel/core.c

5081

for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {

arch/x86/events/intel/core.c

5114

for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {

arch/x86/events/intel/core.c

5616

size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);

arch/x86/events/intel/ds.c

1802

if (WARN_ON(event->hw.idx < 0 || event->hw.idx >= X86_PMC_IDX_MAX))

arch/x86/events/intel/ds.c

3003

for_each_set_bit(bit, (unsigned long *)&pebs_enabled, X86_PMC_IDX_MAX) {

arch/x86/events/intel/ds.c

3138

for_each_set_bit(bit, (unsigned long *)&pebs_status, X86_PMC_IDX_MAX) {

arch/x86/events/intel/ds.c

3165

for_each_set_bit(bit, (unsigned long *)&mask, X86_PMC_IDX_MAX) {

arch/x86/events/intel/ds.c

3242

intel_pmu_pebs_event_update_no_drain(cpuc, X86_PMC_IDX_MAX);

arch/x86/events/intel/knc.c

243

for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {

arch/x86/events/intel/lbr.c

953

int i, j, pos = 0, order[X86_PMC_IDX_MAX];

arch/x86/events/intel/p4.c

1003

for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {

arch/x86/events/intel/p4.c

1045

for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {

arch/x86/events/intel/p4.c

1243

unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];

arch/x86/events/intel/p4.c

1253

bitmap_zero(used_mask, X86_PMC_IDX_MAX);

arch/x86/events/intel/p4.c

1399

for_each_set_bit(i, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {

arch/x86/events/intel/p4.c

924

for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {

arch/x86/events/intel/p4.c

988

static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(X86_PMC_IDX_MAX)], p4_running);

arch/x86/events/perf_event.h

1183

DECLARE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);

arch/x86/events/perf_event.h

143

struct perf_event *owners[X86_PMC_IDX_MAX];

arch/x86/events/perf_event.h

144

struct event_constraint event_constraints[X86_PMC_IDX_MAX];

arch/x86/events/perf_event.h

226

enum intel_excl_state_type state[X86_PMC_IDX_MAX];

arch/x86/events/perf_event.h

269

struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */

arch/x86/events/perf_event.h

270

unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];

arch/x86/events/perf_event.h

271

unsigned long dirty[BITS_TO_LONGS(X86_PMC_IDX_MAX)];

arch/x86/events/perf_event.h

281

int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */

arch/x86/events/perf_event.h

282

u64 tags[X86_PMC_IDX_MAX];

arch/x86/events/perf_event.h

284

struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */

arch/x86/events/perf_event.h

285

struct event_constraint *event_constraint[X86_PMC_IDX_MAX];

arch/x86/events/perf_event.h

316

u64 acr_cfg_b[X86_PMC_IDX_MAX];

arch/x86/events/perf_event.h

317

u64 acr_cfg_c[X86_PMC_IDX_MAX];

arch/x86/events/perf_event.h

319

u64 cfg_c_val[X86_PMC_IDX_MAX];

arch/x86/events/perf_event.h

344

struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX];

arch/x86/events/perf_event.h

58

unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];

arch/x86/events/perf_event.h

742

unsigned long cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];

arch/x86/events/perf_event.h

746

unsigned long fixed_cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];

arch/x86/events/perf_event.h

751

unsigned long acr_cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];

arch/x86/events/perf_event.h

755

unsigned long acr_cause_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];

arch/x86/events/perf_event.h

855

unsigned long cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];

arch/x86/events/perf_event.h

859

unsigned long fixed_cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];

arch/x86/events/perf_event.h

863

unsigned long acr_cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];

arch/x86/events/perf_event.h

867

unsigned long acr_cause_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];

arch/x86/events/zhaoxin/core.c

387

for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {

arch/x86/include/asm/kvm_host.h

587

DECLARE_BITMAP(reprogram_pmi, X86_PMC_IDX_MAX);

arch/x86/include/asm/kvm_host.h

590

DECLARE_BITMAP(all_valid_pmc_idx, X86_PMC_IDX_MAX);

arch/x86/include/asm/kvm_host.h

591

DECLARE_BITMAP(pmc_in_use, X86_PMC_IDX_MAX);

arch/x86/include/asm/kvm_host.h

593

DECLARE_BITMAP(pmc_counting_instructions, X86_PMC_IDX_MAX);

arch/x86/include/asm/kvm_host.h

594

DECLARE_BITMAP(pmc_counting_branches, X86_PMC_IDX_MAX);

arch/x86/kvm/pmu.c

1011

DECLARE_BITMAP(bitmask, X86_PMC_IDX_MAX);

arch/x86/kvm/pmu.c

1017

pmu->pmc_in_use, X86_PMC_IDX_MAX);

arch/x86/kvm/pmu.c

1026

bitmap_zero(pmu->pmc_in_use, X86_PMC_IDX_MAX);

arch/x86/kvm/pmu.c

1105

DECLARE_BITMAP(bitmap, X86_PMC_IDX_MAX);

arch/x86/kvm/pmu.c

1110

BUILD_BUG_ON(sizeof(pmu->global_ctrl) * BITS_PER_BYTE != X86_PMC_IDX_MAX);

arch/x86/kvm/pmu.c

1112

if (bitmap_empty(event_pmcs, X86_PMC_IDX_MAX))

arch/x86/kvm/pmu.c

1116

bitmap_copy(bitmap, event_pmcs, X86_PMC_IDX_MAX);

arch/x86/kvm/pmu.c

1118

(unsigned long *)&pmu->global_ctrl, X86_PMC_IDX_MAX))

arch/x86/kvm/pmu.c

636

DECLARE_BITMAP(bitmap, X86_PMC_IDX_MAX);

arch/x86/kvm/pmu.c

641

bitmap_copy(bitmap, pmu->reprogram_pmi, X86_PMC_IDX_MAX);

arch/x86/kvm/pmu.c

923

bitmap_zero(pmu->reprogram_pmi, X86_PMC_IDX_MAX);

arch/x86/kvm/pmu.c

972

bitmap_zero(pmu->all_valid_pmc_idx, X86_PMC_IDX_MAX);

arch/x86/kvm/pmu.h

106

for_each_set_bit(i, bitmap, X86_PMC_IDX_MAX) \

arch/x86/kvm/pmu.h

217

for_each_set_bit(bit, (unsigned long *)&diff, X86_PMC_IDX_MAX)

arch/x86/kvm/pmu.h

244

X86_PMC_IDX_MAX);