X86_CR4_LA57
if (l5_required == !!(native_read_cr4() & X86_CR4_LA57))
if (!(native_read_cr4() & X86_CR4_LA57))
| X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \
return (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_LA57) ? 57 : 48;
#define KVM_MMU_CR4_ROLE_BITS (X86_CR4_PSE | X86_CR4_PAE | X86_CR4_LA57 | \
BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, la57, X86_CR4_LA57);
u8 l1_address_bits_on_exit = (vmcs12->host_cr4 & X86_CR4_LA57) ? 57 : 48;
cr4_fixed1_update(X86_CR4_LA57, ecx, feature_bit(LA57));
lam_bit = kvm_is_cr4_bit_set(vcpu, X86_CR4_LA57) ? 56 : 47;
if ((cr4 ^ old_cr4) & X86_CR4_LA57)
return kvm_is_cr4_bit_set(vcpu, X86_CR4_LA57) ? 57 : 48;
__reserved_bits |= X86_CR4_LA57; \
bool have_la57 = native_read_cr4() & X86_CR4_LA57;
sregs.cr4 |= X86_CR4_LA57;
TEST_INVALID_CR_BIT(vcpu, cr4, sregs, X86_CR4_LA57);
cr4 |= X86_CR4_LA57;
guest_cr4 &= ~X86_CR4_LA57;