X2APIC_ENABLE
return msr & X2APIC_ENABLE;
if (!(msr & X2APIC_ENABLE))
wrmsrq(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE));
wrmsrq(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE);
if (msr & X2APIC_ENABLE)
wrmsrq(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
if ((old_value ^ value) & X2APIC_ENABLE) {
if (value & X2APIC_ENABLE)
if ((old_value ^ value) & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) {
(guest_cpu_cap_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
return apic_base & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
LAPIC_MODE_INVALID = X2APIC_ENABLE,
LAPIC_MODE_X2APIC = MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE,
if (CC(vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8))
val &= ~X2APIC_ENABLE;
#define LAPIC_X2APIC (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)
wrmsr(MSR_IA32_APICBASE, apicbase | X2APIC_ENABLE);
expected = apic_base & X2APIC_ENABLE ? vcpu->id : vcpu->id << 24;
(apic_base & X2APIC_ENABLE) ? "x2APIC" : "xAPIC",
TEST_ASSERT(!(apic_base & X2APIC_ENABLE),
__test_apic_id(vcpus[i], apic_base | X2APIC_ENABLE);
vcpu_set_msr(vcpu, MSR_IA32_APICBASE, MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);