X2
#define X3(x...) X2(x), x
#define X4(x...) X2(x), X2(x)
#define X6(x...) X4(x), X2(x)
X2(N), GP(SrcReg | DstMem | ModRM | Mov | Aligned, &pfx_0f_e7_0f_38_2a), N, N, N, N, N,
#define OP(X1, X2, X3, X4, rbase) \
X2 ^= t1
#define SLP_VEC(X0, X1, X2, X3, X4) { \
cpu_to_le32(X2), \
#define SLP_VEC(X0, X1, X2, X3, X4) {cpu_to_le32(X0), \
cpu_to_le32(X2), \
I1(X1); I1(X2); I1(Y1); I1(Y2); I1(Z1); I1(Z2);
LOCK(X2); /* this one should fail */
RL(X2); // this one should NOT fail
RSL(X2); // this one should fail
WL(X2); // this one should fail
WSL(X2); // this one should fail
RL(X2); // this one should fail
RSL(X2); // this one should fail