drivers/clk/xilinx/clk-xlnx-clock-wizard.c

1016

clk_wzrd->base, WZRD_CLK_CFG_REG(is_versal, 3),

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

1025

edge = !!(readl(clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 0)) &

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

1027

regl = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 1)) &

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

1029

regh = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 1)) &

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

1036

regl = readl(clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 51)) &

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

1039

regl = readl(clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 48)) &

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

1049

clk_wzrd->base, WZRD_CLK_CFG_REG(is_versal, 3),

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

1057

reg = readl(clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 0));

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

1083

edged = !!(readl(clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 20)) &

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

1085

regld = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 21)) &

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

1087

reghd = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 21)) &

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

1097

ctrl_reg = clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 0);

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

1120

(WZRD_CLK_CFG_REG(is_versal, 2) + i * 8),

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

1130

(WZRD_CLK_CFG_REG(is_versal, 2) + i * 12),

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

1138

(WZRD_CLK_CFG_REG(is_versal, 2) + i * 12),

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

455

writel(0, divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_4));

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

460

regval1 = readl(divider->base + WZRD_CLK_CFG_REG(1,

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

468

writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

471

writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

478

writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

481

writel(regval1, divider->base + WZRD_CLK_CFG_REG(1, WZRD_DIVCLK));

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

485

regval1 = readl(divider->base + WZRD_CLK_CFG_REG(1,

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

499

writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

502

writel(regval, divider->base + WZRD_CLK_CFG_REG(1,

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

524

writel(reg, divider->base + WZRD_CLK_CFG_REG(0, 2));

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

528

writel(reg, divider->base + WZRD_CLK_CFG_REG(0, 0));

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

529

writel(0, divider->base + WZRD_CLK_CFG_REG(0, 3));

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

573

reg = readl(divider->base + WZRD_CLK_CFG_REG(0, 0));

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

577

reg = readl(divider->base + WZRD_CLK_CFG_REG(0, 2));

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

592

edge = !!(readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_1)) &

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

595

reg = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_2));

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

603

regl = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_4)) &

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

606

regl = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_3))

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

615

reg = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKOUT0_1));

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

620

reg = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKOUT0_2));

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

635

edged = !!(readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_DESKEW_2)) &

drivers/clk/xilinx/clk-xlnx-clock-wizard.c

637

reg = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_DIVCLK));