WR_CONFIRM
WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
WR_CONFIRM) |
WR_CONFIRM) |
cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
cmd = WR_CONFIRM;
WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
WR_CONFIRM) |
cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
cmd = WR_CONFIRM;
ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
cmd = WR_CONFIRM;
ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
cmd = WR_CONFIRM;
WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
cmd = WR_CONFIRM;
WR_CONFIRM) |
WR_CONFIRM) |
ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
(wc ? WR_CONFIRM : 0));
ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
WR_CONFIRM) |
WR_CONFIRM) |
cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
cmd = WR_CONFIRM;
cmd = WR_CONFIRM;
WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
cmd = WR_CONFIRM;
(wc ? WR_CONFIRM : 0));
ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;