WRITE_RPS1
WRITE_RPS1(CMD_WR_REG | (1 << 8) | (MC2/4));
WRITE_RPS1(MASK_28 | MASK_12);
WRITE_RPS1(CMD_WR_REG_MASK | (MC1/4));
WRITE_RPS1(MASK_04 | MASK_20); /* => mask */
WRITE_RPS1(MASK_04 | MASK_20); /* => values */
WRITE_RPS1(CMD_PAUSE | o_wait);
WRITE_RPS1(CMD_PAUSE | e_wait);
WRITE_RPS1(CMD_INTERRUPT);
WRITE_RPS1(CMD_STOP);
WRITE_RPS1(CMD_WR_REG | (1 << 8) | (BRS_CTRL/4));
WRITE_RPS1(0xc000008c);
WRITE_RPS1(CMD_PAUSE | CMD_OAN | CMD_SIG1 | CMD_E_FID_B);
WRITE_RPS1(CMD_PAUSE | CMD_OAN | CMD_SIG1 | CMD_O_FID_B);
WRITE_RPS1(CMD_PAUSE | MASK_10);
WRITE_RPS1(CMD_UPLOAD | MASK_08);
WRITE_RPS1(CMD_WR_REG | (1 << 8) | (BRS_CTRL/4));
WRITE_RPS1(((1728-(vbi_pixel_to_capture)) << 7) | MASK_19);
WRITE_RPS1(CMD_PAUSE | MASK_08);
WRITE_RPS1(CMD_UPLOAD | MASK_08);
WRITE_RPS1(CMD_WR_REG | (1 << 8) | (NUM_LINE_BYTE3/4));
WRITE_RPS1((2 << 16) | (vbi_pixel_to_capture));
WRITE_RPS1(CMD_WR_REG | (1 << 8) | (BRS_CTRL/4));
WRITE_RPS1((540 << 7) | (5 << 19)); // 5 == vbi_start
WRITE_RPS1(CMD_PAUSE | MASK_08);
WRITE_RPS1(CMD_UPLOAD | MASK_08 | MASK_04);
WRITE_RPS1(CMD_WR_REG | (1 << 8) | (MC1/4));
WRITE_RPS1(MASK_20 | MASK_04);
WRITE_RPS1(CMD_INTERRUPT);
WRITE_RPS1(CMD_STOP);
WRITE_RPS1(CMD_PAUSE | EVT_VBI_B);
WRITE_RPS1(CMD_WR_REG_MASK | (GPIO_CTRL >> 2));
WRITE_RPS1(GPIO3_MSK);
WRITE_RPS1(SAA7146_GPIO_OUTLO << 24);
WRITE_RPS1(CMD_INTERRUPT);
WRITE_RPS1(CMD_STOP);
WRITE_RPS1(CMD_JUMP);
WRITE_RPS1(dev->d_rps1.dma_handle);
WRITE_RPS1(CMD_PAUSE | EVT_HS);
WRITE_RPS1(CMD_WR_REG_MASK | (GPIO_CTRL >> 2));
WRITE_RPS1(GPIO3_MSK);
WRITE_RPS1(SAA7146_GPIO_OUTHI << 24);
WRITE_RPS1(CMD_INTERRUPT);
WRITE_RPS1(CMD_PAUSE | RPS_INV | EVT_HS);
WRITE_RPS1(CMD_WR_REG_MASK | (GPIO_CTRL >> 2));
WRITE_RPS1(GPIO3_MSK);
WRITE_RPS1(SAA7146_GPIO_OUTLO << 24);
WRITE_RPS1(CMD_INTERRUPT);
WRITE_RPS1(CMD_JUMP);
WRITE_RPS1(dev->d_rps1.dma_handle);