WRITE_REG32
WRITE_REG32(stat, d->hba.base_addr + LBA_ERROR_CONFIG);
WRITE_REG32(stat | HF_ENABLE, d->hba.base_addr + LBA_STAT_CTL);
WRITE_REG32(stat & ~HF_ENABLE, d->hba.base_addr + LBA_STAT_CTL);
WRITE_REG32(0x3, d->hba.base_addr + LBA_ARB_MASK);
WRITE_REG32( imask, base_addr + LBA_IMASK);
WRITE_REG32( ibase, base_addr + LBA_IBASE);
WRITE_REG32(0x1, d->hba.base_addr + LBA_ARB_MASK); \
WRITE_REG32(error_config | LBA_SMART_MODE, d->hba.base_addr + LBA_ERROR_CONFIG); \
WRITE_REG32(tok | PCI_VENDOR_ID, (d)->hba.base_addr + LBA_PCI_CFG_ADDR);\
WRITE_REG32(~0, (d)->hba.base_addr + LBA_PCI_CFG_DATA); \
WRITE_REG32(status_control | CLEAR_ERRLOG_ENABLE, base + LBA_STAT_CTL); \
WRITE_REG32(status_control | CLEAR_ERRLOG, base + LBA_STAT_CTL); \
WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR);
WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
WRITE_REG32(status_control, base + LBA_STAT_CTL); \
WRITE_REG32(error_config, base + LBA_ERROR_CONFIG); \
WRITE_REG32(arb_mask, base + LBA_ARB_MASK); \
case 4: WRITE_REG32(data, data_reg); break;
case 4: WRITE_REG32(data, d->hba.base_addr + LBA_PCI_CFG_DATA);
WRITE_REG32(data, data_reg);
#define WRITE_REG(value, addr) WRITE_REG32(value, addr)