WRITEREG
WRITEREG(acon1, ACON1);
WRITEREG(3 * (BurstA1_in) + 3 * (ThreshA1_in) +
WRITEREG((EAP << 16) | EAP, MC1);
WRITEREG((EI2C << 16) | EI2C, MC1);
WRITEREG(A1_out | A2_out | A1_in | IIC_S | IIC_E, IER);
WRITEREG(acon2, ACON2);
WRITEREG(tsl1[i], TSL1 + (i * 4));
WRITEREG(tsl2[i], TSL2 + (i * 4));
WRITEREG(dw_page, PageA2_out);
WRITEREG(dma_addr, BaseA2_out);
WRITEREG(dma_addr + buffer_size, ProtA2_out);
WRITEREG(dw_page, PageA1_out);
WRITEREG(dma_addr, BaseA1_out);
WRITEREG(dma_addr + buffer_size, ProtA1_out);
WRITEREG(dw_page, PageA1_in);
WRITEREG(dma_addr, BaseA1_in);
WRITEREG(dma_addr + buffer_size, ProtA1_in);
WRITEREG((TR_E_A2_OUT << 16) | TR_E_A2_OUT, MC1);
WRITEREG(acon1, ACON1);
WRITEREG((TR_E_A1_OUT << 16) | TR_E_A1_OUT, MC1);
WRITEREG(acon1, ACON1);
WRITEREG(acon1, ACON1);
WRITEREG((TR_E_A2_OUT << 16), MC1);
WRITEREG(acon1, ACON1);
WRITEREG((TR_E_A1_OUT << 16), MC1);
WRITEREG((TR_E_A1_IN << 16) | TR_E_A1_IN, MC1);
WRITEREG((TR_E_A1_IN << 16), MC1);
WRITEREG(isr, ISR);
WRITEREG(0x100, IICSTA);
WRITEREG(0, IER);
WRITEREG(0x40, GPIO_CTRL);
WRITEREG(0x50, GPIO_CTRL);
WRITEREG((MRST_N << 16), MC1);
WRITEREG(0, IER);
WRITEREG((MRST_N << 16), MC1);