WREG8
WREG8(AI_MAIBOX_CONTROL_RCV_OFFSET_BYTE, 2);
WREG8(AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE, val ? 1 : 0);
WREG8(NV_MAIBOX_CONTROL_RCV_OFFSET_BYTE, 2);
WREG8(NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE, val ? 1 : 0);
WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL);
WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
WREG8(DAC_INDEX, MGA1064_SPAREREG);
WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
WREG8(DAC_DATA, tmp);
WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
WREG8(DAC_DATA, tmp);
WREG8(DAC_INDEX, MGA1064_SPAREREG);
WREG8(DAC_DATA, tmp);
WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL);
WREG8(MGA_MISC_OUT, misc);
WREG8(GFX_INDEX, reg); \
WREG8(GFX_DATA, v); \
WREG8(DAC_INDEX, reg); \
WREG8(DAC_INDEX, reg); \
WREG8(DAC_DATA, v); \
WREG8(MGA_MISC_OUT, v)
WREG8(ATTR_INDEX, reg); \
WREG8(ATTR_DATA, v); \
WREG8(MGAREG_SEQ_INDEX, reg); \
WREG8(MGAREG_SEQ_INDEX, reg); \
WREG8(MGAREG_SEQ_DATA, v); \
WREG8(MGAREG_CRTC_INDEX, reg); \
WREG8(MGAREG_CRTC_INDEX, reg); \
WREG8(MGAREG_CRTC_DATA, v); \
WREG8(MGAREG_CRTCEXT_INDEX, reg); \
WREG8(MGAREG_CRTCEXT_INDEX, reg); \
WREG8(MGAREG_CRTCEXT_DATA, v); \
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
WREG8(DAC_DATA, tmp);
WREG8(MGAREG_MEM_MISC_WRITE, tmp);
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
WREG8(DAC_DATA, tmp);
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
WREG8(DAC_DATA, tmp);
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
WREG8(DAC_DATA, tmp);
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
WREG8(DAC_DATA, tmp);
WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
WREG8(DAC_DATA, tmp);
WREG8(MGAREG_MEM_MISC_WRITE, tmp);
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
WREG8(DAC_DATA, tmp);
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
WREG8(DAC_DATA, tmp);
WREG8(MGAREG_MEM_MISC_WRITE, tmp);
WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
WREG8(DAC_DATA, tmp & ~0x40);
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
WREG8(DAC_DATA, tmp);
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
WREG8(DAC_DATA, tmp);
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
WREG8(DAC_DATA, tmp);
WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
WREG8(DAC_DATA, tmp | 0x40);
WREG8(MGAREG_MEM_MISC_WRITE, tmp);
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
WREG8(DAC_DATA, tmp);
WREG8(MGAREG_CRTC_INDEX, 0x1e);
WREG8(MGAREG_CRTC_DATA, tmp+1);
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
WREG8(DAC_DATA, tmp);
WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
WREG8(DAC_DATA, tmp);
WREG8(MGAREG_MEM_MISC_WRITE, tmp);
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
WREG8(DAC_DATA, tmp);
WREG8(DAC_INDEX, MGA1064_VREF_CTL);
WREG8(DAC_DATA, tmp);
WREG8(DAC_INDEX, MGA1064_VREF_CTL);
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
WREG8(DAC_DATA, tmp);
WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
WREG8(DAC_DATA, tmp);
WREG8(MGAREG_SEQ_INDEX, 1);
WREG8(MGAREG_SEQ_DATA, tmp);
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
WREG8(DAC_DATA, tmp);
WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
WREG8(MGA_MISC_OUT, misc);
WREG8(MGA_MISC_OUT, misc);
WREG8(DAC_INDEX + MGA1064_INDEX, i8);
WREG8(DAC_INDEX + MGA1064_COL_PAL, r8);
WREG8(DAC_INDEX + MGA1064_COL_PAL, g8);
WREG8(DAC_INDEX + MGA1064_COL_PAL, b8);
WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
WREG8(RADEON_PALETTE_INDEX, 0);
WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
WREG8(RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_TEST_CNTL);
WREG8(RADEON_CLOCK_CNTL_DATA + 3, 0);