drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

100

WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_INSTR_BASE_HI, 0);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

103

WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_INSTR_MASK_LO, lower_32_bits(data));

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

104

WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_INSTR_MASK_HI, upper_32_bits(data));

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

108

WREG32_SOC15_UMSCH(regVCN_MES_IC_BASE_LO, lower_32_bits(data));

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

109

WREG32_SOC15_UMSCH(regVCN_MES_IC_BASE_HI, upper_32_bits(data));

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

111

WREG32_SOC15_UMSCH(regVCN_MES_MIBOUND_LO, 0x1FFFFF);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

113

WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_BASE0_LO,

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

115

WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_BASE0_HI,

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

118

WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_MASK0_LO,

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

120

WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_MASK0_HI, 0);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

124

WREG32_SOC15_UMSCH(regVCN_MES_DC_BASE_LO, lower_32_bits(data));

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

125

WREG32_SOC15_UMSCH(regVCN_MES_DC_BASE_HI, upper_32_bits(data));

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

127

WREG32_SOC15_UMSCH(regVCN_MES_MDBOUND_LO, 0x3FFFF);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

132

WREG32_SOC15_UMSCH(regUVD_UMSCH_FORCE, data);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

137

WREG32_SOC15_UMSCH(regVCN_MES_IC_OP_CNTL, data);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

141

WREG32_SOC15_UMSCH(regVCN_MES_IC_OP_CNTL, data);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

143

WREG32_SOC15_UMSCH(regVCN_MES_GP0_LO, 0);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

144

WREG32_SOC15_UMSCH(regVCN_MES_GP0_HI, 0);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

147

WREG32_SOC15_UMSCH(regVCN_MES_GP0_LO, lower_32_bits(umsch->log_gpu_addr));

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

148

WREG32_SOC15_UMSCH(regVCN_MES_GP0_HI, upper_32_bits(umsch->log_gpu_addr));

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

151

WREG32_SOC15_UMSCH(regVCN_MES_GP1_LO, 0);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

152

WREG32_SOC15_UMSCH(regVCN_MES_GP1_HI, 0);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

159

WREG32_SOC15_UMSCH(regVCN_MES_CNTL, data);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

74

WREG32_SOC15_UMSCH(regUMSCH_MES_RESET_CTRL, data);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

81

WREG32_SOC15_UMSCH(regVCN_MES_CNTL, data);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

87

WREG32_SOC15_UMSCH(regVCN_MES_IC_BASE_CNTL, data);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

89

WREG32_SOC15_UMSCH(regVCN_MES_INTR_ROUTINE_START,

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

91

WREG32_SOC15_UMSCH(regVCN_MES_INTR_ROUTINE_START_HI,

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

94

WREG32_SOC15_UMSCH(regVCN_MES_PRGRM_CNTR_START,

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

96

WREG32_SOC15_UMSCH(regVCN_MES_PRGRM_CNTR_START_HI,

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

99

WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_INSTR_BASE_LO, 0);