drivers/gpu/drm/amd/amdgpu/si.c

1879

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);

drivers/gpu/drm/amd/amdgpu/si.c

1884

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);

drivers/gpu/drm/amd/amdgpu/si.c

1896

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);

drivers/gpu/drm/amd/amdgpu/si.c

1912

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,

drivers/gpu/drm/amd/amdgpu/si.c

1917

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_BYPASS_EN_MASK,

drivers/gpu/drm/amd/amdgpu/si.c

1930

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK,

drivers/gpu/drm/amd/amdgpu/si.c

1942

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK);

drivers/gpu/drm/amd/amdgpu/si.c

1945

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_VCO_MODE_MASK,

drivers/gpu/drm/amd/amdgpu/si.c

1949

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK,

drivers/gpu/drm/amd/amdgpu/si.c

1951

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_SLEEP_MASK);

drivers/gpu/drm/amd/amdgpu/si.c

1954

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK);

drivers/gpu/drm/amd/amdgpu/si.c

1963

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_RESET_MASK, ~VCEPLL_RESET_MASK);

drivers/gpu/drm/amd/amdgpu/si.c

1966

WREG32_SMC_P(CG_VCEPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);

drivers/gpu/drm/amd/amdgpu/si.c

1969

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_3,

drivers/gpu/drm/amd/amdgpu/si.c

1974

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_REF_DIV_MASK);

drivers/gpu/drm/amd/amdgpu/si.c

1977

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,

drivers/gpu/drm/amd/amdgpu/si.c

1985

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK);

drivers/gpu/drm/amd/amdgpu/si.c

1990

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_BYPASS_EN_MASK);

drivers/gpu/drm/amd/amdgpu/si.c

1997

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,

drivers/gpu/drm/radeon/si.c

7434

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);

drivers/gpu/drm/radeon/si.c

7439

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);

drivers/gpu/drm/radeon/si.c

7450

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);

drivers/gpu/drm/radeon/si.c

7466

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,

drivers/gpu/drm/radeon/si.c

7471

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_BYPASS_EN_MASK,

drivers/gpu/drm/radeon/si.c

7476

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK,

drivers/gpu/drm/radeon/si.c

7488

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK);

drivers/gpu/drm/radeon/si.c

7491

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_VCO_MODE_MASK,

drivers/gpu/drm/radeon/si.c

7495

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK,

drivers/gpu/drm/radeon/si.c

7497

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_SLEEP_MASK);

drivers/gpu/drm/radeon/si.c

7500

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK);

drivers/gpu/drm/radeon/si.c

7509

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_RESET_MASK, ~VCEPLL_RESET_MASK);

drivers/gpu/drm/radeon/si.c

7512

WREG32_SMC_P(CG_VCEPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);

drivers/gpu/drm/radeon/si.c

7515

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_3, VCEPLL_FB_DIV(fb_div), ~VCEPLL_FB_DIV_MASK);

drivers/gpu/drm/radeon/si.c

7518

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_REF_DIV_MASK);

drivers/gpu/drm/radeon/si.c

7521

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,

drivers/gpu/drm/radeon/si.c

7529

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK);

drivers/gpu/drm/radeon/si.c

7534

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_BYPASS_EN_MASK);

drivers/gpu/drm/radeon/si.c

7541

WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,