WREG32_PLL
WREG32_PLL(reg, tmp_); \
WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
WREG32_PLL(SCLK_CNTL, sclk_cntl);
WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
WREG32_PLL(0x000D, tmp);
WREG32_PLL(reg, tmp_); \
WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
WREG32_PLL(RADEON_SPLL_CNTL, tmp);
WREG32_PLL(RADEON_SPLL_CNTL, tmp);
WREG32_PLL(RADEON_M_SPLL_REF_FB_DIV, tmp);
WREG32_PLL(RADEON_SPLL_CNTL, tmp);
WREG32_PLL(RADEON_SPLL_CNTL, tmp);
WREG32_PLL(RADEON_SPLL_CNTL, tmp);
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
WREG32_PLL(R300_SCLK_CNTL2, tmp);
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
WREG32_PLL(RADEON_MCLK_MISC, tmp);
WREG32_PLL(RADEON_MCLK_CNTL, tmp);
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
WREG32_PLL(R300_SCLK_CNTL2, tmp);
WREG32_PLL(RADEON_CLK_PWRMGT_CNTL, tmp);
WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
WREG32_PLL(R300_SCLK_CNTL2, tmp);
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
WREG32_PLL(RADEON_MCLK_CNTL, tmp);
WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
WREG32_PLL(RADEON_SCLK_CNTL, tmp);
WREG32_PLL(R300_SCLK_CNTL2, tmp);
WREG32_PLL(RADEON_MCLK_CNTL, tmp);
WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
WREG32_PLL(reg, val);
WREG32_PLL(addr, val);
WREG32_PLL(addr, tmp);
WREG32_PLL(RADEON_MCLK_CNTL,
WREG32_PLL
WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl);
WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl);
WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test & ~RADEON_PLL_MASK_READ_B);
WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test);
WREG32_PLL(RADEON_TV_PLL_CNTL, tv_pll_cntl);
WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length);
WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl);
WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl);
WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl);
WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl);
WREG32_PLL(0x000D, tmp);
WREG32_PLL(R_00000F_CP_DYN_CNTL,
WREG32_PLL(R_000011_E2_DYN_CNTL,
WREG32_PLL(R_000013_IDCT_DYN_CNTL,