WREG32_PLL_P
WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
WREG32_PLL_P(RADEON_PPLL_REF_DIV,
WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
WREG32_PLL_P(RADEON_P2PLL_CNTL,
WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
WREG32_PLL_P(RADEON_P2PLL_DIV_0,
WREG32_PLL_P(RADEON_P2PLL_DIV_0,
WREG32_PLL_P(RADEON_P2PLL_CNTL,
WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
WREG32_PLL_P(RADEON_PPLL_CNTL,
WREG32_PLL_P(RADEON_PPLL_REF_DIV,
WREG32_PLL_P(RADEON_PPLL_REF_DIV,
WREG32_PLL_P(RADEON_PPLL_REF_DIV,
WREG32_PLL_P(RADEON_PPLL_DIV_3,
WREG32_PLL_P(RADEON_PPLL_DIV_3,
WREG32_PLL_P(RADEON_PPLL_CNTL,
WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVCLK_SRC_SEL_TVPLL);
WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVPLL_RESET, ~RADEON_TVPLL_RESET);
WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_RESET);
WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~0xf);
WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVCLK_SRC_SEL_TVPLL, ~RADEON_TVCLK_SRC_SEL_TVPLL);
WREG32_PLL_P(RADEON_TV_PLL_CNTL1, (1 << RADEON_TVPDC_SHIFT), ~RADEON_TVPDC_MASK);
WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_SLEEP);