drivers/accel/habanalabs/common/habanalabs.h

2640

#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)

drivers/accel/habanalabs/common/habanalabs.h

2641

#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))

drivers/accel/habanalabs/common/habanalabs.h

2643

#define RMWREG32_SHIFTED(reg, val, mask) WREG32_P(reg, val, ~(mask))

drivers/gpu/drm/amd/amdgpu/amdgpu.h

1404

#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)

drivers/gpu/drm/amd/amdgpu/amdgpu.h

1405

#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

2047

WREG32_P(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset,

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

1673

WREG32_P(mmHDMI_INFOFRAME_CONTROL1 + offset,

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

1959

WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset,

drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c

137

WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);

drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c

134

WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);

drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c

130

WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);

drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c

223

WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

1081

WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

1273

WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1451

WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

650

WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);

drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c

354

WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 0,

drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c

358

WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmJPEG_SYS_INT_EN),

drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c

389

WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL),

drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c

345

WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS), 0,

drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c

358

WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL), 0,

drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c

362

WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmJPEG_SYS_INT_EN),

drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c

403

WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL),

drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c

410

WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS),

drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c

307

WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), 0,

drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c

311

WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), 0,

drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c

320

WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS),

drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c

374

WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 0,

drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c

378

WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmJPEG_SYS_INT_EN),

drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c

409

WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL),

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c

344

WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0,

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c

348

WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0,

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c

357

WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS),

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c

410

WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 0,

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c

414

WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regJPEG_SYS_INT_EN),

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c

569

WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL),

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

555

WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS),

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

568

WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 0,

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

579

WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regJPEG_SYS_INT_EN),

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

639

WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL),

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

646

WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS),

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c

384

WREG32_P(SOC15_REG_OFFSET(JPEG, inst, regUVD_JPEG_POWER_STATUS), 0,

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c

388

WREG32_P(SOC15_REG_OFFSET(JPEG, inst, regUVD_JPEG_POWER_STATUS), 0,

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c

397

WREG32_P(SOC15_REG_OFFSET(JPEG, inst, regUVD_JPEG_POWER_STATUS),

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c

540

WREG32_P(SOC15_REG_OFFSET(JPEG, i, regUVD_JMI_CNTL), 0,

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c

544

WREG32_P(SOC15_REG_OFFSET(JPEG, i, regJPEG_SYS_INT_EN),

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c

585

WREG32_P(SOC15_REG_OFFSET(JPEG, i, regUVD_JMI_CNTL),

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c

279

WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0,

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c

288

WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS),

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c

451

WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 0,

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c

455

WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regJPEG_SYS_INT_EN),

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c

494

WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL),

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

371

WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS), 0,

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

375

WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS), 0,

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

383

WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 0,

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

391

WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL),

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

396

WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS),

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

413

WREG32_P(reg, data, mask);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

417

WREG32_P(reg, data, mask);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c

262

WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0,

drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c

271

WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS),

drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c

434

WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 0,

drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c

438

WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regJPEG_SYS_INT_EN),

drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c

477

WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL),

drivers/gpu/drm/amd/amdgpu/si.c

1652

WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);

drivers/gpu/drm/amd/amdgpu/si.c

1657

WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);

drivers/gpu/drm/amd/amdgpu/si.c

1669

WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);

drivers/gpu/drm/amd/amdgpu/si.c

1789

WREG32_P(CG_UPLL_FUNC_CNTL_2,

drivers/gpu/drm/amd/amdgpu/si.c

1794

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);

drivers/gpu/drm/amd/amdgpu/si.c

1808

WREG32_P(CG_UPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK);

drivers/gpu/drm/amd/amdgpu/si.c

1811

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);

drivers/gpu/drm/amd/amdgpu/si.c

1814

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);

drivers/gpu/drm/amd/amdgpu/si.c

1817

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);

drivers/gpu/drm/amd/amdgpu/si.c

1826

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);

drivers/gpu/drm/amd/amdgpu/si.c

1829

WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);

drivers/gpu/drm/amd/amdgpu/si.c

1832

WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK);

drivers/gpu/drm/amd/amdgpu/si.c

1835

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);

drivers/gpu/drm/amd/amdgpu/si.c

1838

WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9);

drivers/gpu/drm/amd/amdgpu/si.c

1840

WREG32_P(CG_UPLL_FUNC_CNTL_4,

drivers/gpu/drm/amd/amdgpu/si.c

1845

WREG32_P(CG_UPLL_FUNC_CNTL_2,

drivers/gpu/drm/amd/amdgpu/si.c

1853

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);

drivers/gpu/drm/amd/amdgpu/si.c

1858

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);

drivers/gpu/drm/amd/amdgpu/si.c

1865

WREG32_P(CG_UPLL_FUNC_CNTL_2,

drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c

331

WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2));

drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c

337

WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);

drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c

344

WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));

drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c

372

WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));

drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c

374

WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);

drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c

376

WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);

drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c

378

WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);

drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c

395

WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,

drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c

398

WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);

drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c

409

WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1));

drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c

411

WREG32_P(mmUVD_STATUS, 0, ~(1<<2));

drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c

435

WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f);

drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c

477

WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));

drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c

490

WREG32_P(0x3D49, 0, ~(1 << 2));

drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c

492

WREG32_P(mmUVD_VCPU_CNTL, 0, ~(1 << 9));

drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c

807

WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

293

WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2));

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

299

WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

306

WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

335

WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

337

WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

339

WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

341

WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

358

WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

361

WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

372

WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1));

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

374

WREG32_P(mmUVD_STATUS, 0, ~(1<<2));

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

398

WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f);

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

440

WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

453

WREG32_P(0x3D49, 0, ~(1 << 2));

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

455

WREG32_P(mmUVD_VCPU_CNTL, 0, ~(1 << 9));

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

687

WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

328

WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2));

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

337

WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

340

WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

352

WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

382

WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

401

WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

404

WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

414

WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1));

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

417

WREG32_P(mmUVD_STATUS, 0, ~(2 << 1));

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

448

WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

466

WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

477

WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

608

WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

735

WREG32_P(mmUVD_POWER_STATUS, 0, ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

830

WREG32_P(mmUVD_MASTINT_EN,

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

835

WREG32_P(mmUVD_STATUS, 0, ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

899

WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

910

WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

1040

WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 0,

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

1061

WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET),

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

1065

WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 0,

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

1076

WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN),

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

1081

WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0,

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

1114

WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_RBC_RB_CNTL), 0,

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

1152

WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

1166

WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0,

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

966

WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_POWER_STATUS), 0,

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

981

WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0,

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

985

WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 0,

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

989

WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2),

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

150

WREG32_P(mmVCE_SOFT_RESET,

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

154

WREG32_P(mmVCE_SOFT_RESET, 0,

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

299

WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

303

WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16));

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

304

WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

305

WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

308

WREG32_P(mmVCE_LMI_FW_PERIODIC_CTRL, 0x4, ~0x4);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

312

WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

334

WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

384

WREG32_P(mmVCE_STATUS, 1, ~1);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

404

WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK,

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

407

WREG32_P(mmVCE_SOFT_RESET,

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

415

WREG32_P(mmVCE_SOFT_RESET, 0,

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

450

WREG32_P(mmVCE_LMI_CTRL2, 1 << 8, ~(1 << 8));

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

459

WREG32_P(mmVCE_VCPU_CNTL, 0, ~VCE_VCPU_CNTL__CLK_EN_MASK);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

461

WREG32_P(mmVCE_SOFT_RESET,

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

721

WREG32_P(mmVCE_SYS_INT_EN, val,

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

130

WREG32_P(mmVCE_SOFT_RESET,

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

134

WREG32_P(mmVCE_SOFT_RESET, 0,

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

172

WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16));

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

173

WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

174

WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

178

WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

200

WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

236

WREG32_P(mmVCE_STATUS, 1, ~1);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

265

WREG32_P(mmVCE_STATUS, 0, ~1);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

297

WREG32_P(mmVCE_LMI_CTRL2, 1 << 8, ~(1 << 8));

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

306

WREG32_P(mmVCE_VCPU_CNTL, 0, ~0x80001);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

309

WREG32_P(mmVCE_SOFT_RESET, 1, ~0x1);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

563

WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

306

WREG32_P(mmVCE_VCPU_CNTL, 1, ~0x200001);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

343

WREG32_P(mmVCE_VCPU_CNTL, 0, ~0x200001);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

558

WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16));

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

559

WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

560

WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

564

WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

601

WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

741

WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);

drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

140

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET),

drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

144

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), 0,

drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

366

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), VCE_STATUS__JOB_BUSY_MASK,

drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

369

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL), 1, ~0x200001);

drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

371

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), 0,

drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

378

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), 0, ~VCE_STATUS__JOB_BUSY_MASK);

drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

392

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL), 0, ~0x200001);

drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

395

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET),

drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

640

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_A), 0, ~(1 << 16));

drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

641

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING), 0x1FF000, ~0xFF9FF000);

drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

642

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING), 0x3F, ~0x3F);

drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

646

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CACHE_CTRL), 0x0, ~0x1);

drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

686

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL2), 0x0, ~0x100);

drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

687

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN),

drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

787

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN), val,

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

1157

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

1199

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

1208

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

1212

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

1216

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

1221

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

1266

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

860

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

909

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

913

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

935

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

939

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

950

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

954

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN),

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

993

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1026

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1030

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1070

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1074

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1104

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1108

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1120

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1125

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1205

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1254

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1258

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1263

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1268

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1322

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1351

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

961

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

990

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1009

WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1,

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1116

WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1145

WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1176

WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1190

WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1194

WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1241

WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1245

WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1248

WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1268

WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1272

WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1285

WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN),

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1290

WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1566

WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1617

WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL),

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1622

WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1627

WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1636

WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS),

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1684

WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1710

WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1038

WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1,

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1147

WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1182

WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1222

WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1226

WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1230

WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1279

WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1283

WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1300

WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1304

WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1317

WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN),

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1322

WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1621

WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1671

WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL),

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1676

WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1681

WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1745

WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1779

WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1006

WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1167

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1171

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1175

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1224

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1228

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1255

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1259

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1273

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN),

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1278

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1589

WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1648

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL),

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1653

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1658

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1212

WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1217

WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1221

WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1272

WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1276

WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1295

WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1300

WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1314

WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN),

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1319

WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1386

WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1449

WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL),

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1454

WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1459

WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

857

WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 1,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1079

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1083

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1087

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1136

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1140

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1168

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1172

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1186

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN),

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1191

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1251

WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1311

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL),

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1316

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1321

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

921

WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

1042

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL),

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

1047

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

1052

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

705

WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

833

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

837

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

841

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

864

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

868

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

896

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

900

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

914

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN),

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

919

WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

980

WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1003

WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1007

WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1030

WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1034

WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1062

WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1066

WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1080

WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN),

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1085

WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1154

WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1212

WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL),

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1217

WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1222

WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

681

WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 1,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

999

WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),

drivers/gpu/drm/amd/pm/legacy-dpm/kv_smc.c

86

WREG32_P(mmSMC_IND_ACCESS_CNTL, 0,

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

3129

WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

3134

WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

3139

WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

3144

WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

3152

WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

3819

WREG32_P(mmCG_THERMAL_CTRL, dpm_event_src << CG_THERMAL_CTRL__DPM_EVENT_SRC__SHIFT, ~CG_THERMAL_CTRL__DPM_EVENT_SRC_MASK);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

3821

WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

3823

WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK, ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

3848

WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK, ~GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

3853

WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

3859

WREG32_P(mmSCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

3861

WREG32_P(mmSCLK_PWRMGT_CNTL, SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK, ~SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

4107

WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

4109

WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK, ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

4114

WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__STATIC_PM_EN_MASK, ~GENERAL_PWRMGT__STATIC_PM_EN_MASK);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

4195

WREG32_P(mmMISC_CLK_CNTL, (tmp << MISC_CLK_CNTL__DEEP_SLEEP_CLK_SEL__SHIFT), ~MISC_CLK_CNTL__DEEP_SLEEP_CLK_SEL_MASK);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

4196

WREG32_P(mmCG_SPLL_AUTOSCALE_CNTL, CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_SS_CLEAR_MASK,

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

4243

WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK, ~GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

4245

WREG32_P(mmCG_SPLL_SPREAD_SPECTRUM, 0, ~CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

4246

WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

4276

WREG32_P(mmCG_GIT, R600_GICST_DFLT << CG_GIT__CG_GICST__SHIFT, ~CG_GIT__CG_GICST_MASK);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

4288

WREG32_P(mmSCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_CNTL__FIR_FORCE_TREND_SEL_MASK);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

4290

WREG32_P(mmSCLK_PWRMGT_CNTL, SCLK_PWRMGT_CNTL__FIR_FORCE_TREND_SEL_MASK, ~SCLK_PWRMGT_CNTL__FIR_FORCE_TREND_SEL_MASK);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

4293

WREG32_P(mmSCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_CNTL__FIR_TREND_MODE_MASK);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

4296

WREG32_P(mmSCLK_PWRMGT_CNTL, SCLK_PWRMGT_CNTL__FIR_TREND_MODE_MASK, ~SCLK_PWRMGT_CNTL__FIR_TREND_MODE_MASK);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

6230

WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK, ~GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

6232

WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

6497

WREG32_P(mmCG_THERMAL_INT, (high_temp / 1000) << CG_THERMAL_INT__DIG_THERM_INTH__SHIFT, ~CG_THERMAL_INT__DIG_THERM_INTH_MASK);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

6498

WREG32_P(mmCG_THERMAL_INT, (low_temp / 1000) << CG_THERMAL_INT__DIG_THERM_INTL__SHIFT, ~CG_THERMAL_INT__DIG_THERM_INTL_MASK);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

6499

WREG32_P(mmCG_THERMAL_CTRL, (high_temp / 1000) << CG_THERMAL_CTRL__DIG_THERM_DPM__SHIFT, ~CG_THERMAL_CTRL__DIG_THERM_DPM_MASK);

drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c

257

WREG32_P(mmSMC_IND_ACCESS_CNTL, SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK, ~SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK);

drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c

267

WREG32_P(mmSMC_IND_ACCESS_CNTL, 0, ~SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK);

drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c

48

WREG32_P(mmSMC_IND_ACCESS_CNTL, 0, ~SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK);

drivers/gpu/drm/radeon/atombios_crtc.c

1391

WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/atombios_crtc.c

1597

WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/btc_dpm.c

1351

WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);

drivers/gpu/drm/radeon/btc_dpm.c

1353

WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);

drivers/gpu/drm/radeon/btc_dpm.c

1639

WREG32_P(SCLK_PSKIP_CNTL, PSKIP_ON_ALLOW_STOP_HI(32),

drivers/gpu/drm/radeon/btc_dpm.c

1746

WREG32_P(MC_ARB_RFSH_RATE, POWERMODE0(val), ~POWERMODE0_MASK);

drivers/gpu/drm/radeon/btc_dpm.c

1750

WREG32_P(MC_ARB_BURST_TIME, STATE0(val), ~STATE0_MASK);

drivers/gpu/drm/radeon/btc_dpm.c

1791

WREG32_P(MC_ARB_RFSH_RATE, POWERMODE0(val), ~POWERMODE0_MASK);

drivers/gpu/drm/radeon/btc_dpm.c

1794

WREG32_P(MC_ARB_BURST_TIME, STATE0(val), ~STATE0_MASK);

drivers/gpu/drm/radeon/ci_dpm.c

1455

WREG32_P(MC_SEQ_CNTL_3, CAC_EN, ~CAC_EN);

drivers/gpu/drm/radeon/ci_dpm.c

1501

WREG32_P(BIF_LNCNT_RESET, 0, ~RESET_LNCNT_EN);

drivers/gpu/drm/radeon/ci_smc.c

230

WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0);

drivers/gpu/drm/radeon/ci_smc.c

240

WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);

drivers/gpu/drm/radeon/ci_smc.c

42

WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);

drivers/gpu/drm/radeon/cik.c

7900

WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);

drivers/gpu/drm/radeon/cypress_dpm.c

102

WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);

drivers/gpu/drm/radeon/cypress_dpm.c

103

WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);

drivers/gpu/drm/radeon/cypress_dpm.c

104

WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);

drivers/gpu/drm/radeon/cypress_dpm.c

109

WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_SwitchToMinimumPower),

drivers/gpu/drm/radeon/cypress_dpm.c

1105

WREG32_P(MC_CONFIG_MCD, MC_RD_ENABLE_MCD(i), ~MC_RD_ENABLE_MCD_MASK);

drivers/gpu/drm/radeon/cypress_dpm.c

1106

WREG32_P(MC_CG_CONFIG_MCD, MC_RD_ENABLE_MCD(i), ~MC_RD_ENABLE_MCD_MASK);

drivers/gpu/drm/radeon/cypress_dpm.c

1108

WREG32_P(MC_CONFIG, MC_RD_ENABLE(i), ~MC_RD_ENABLE_MASK);

drivers/gpu/drm/radeon/cypress_dpm.c

1109

WREG32_P(MC_CG_CONFIG, MC_RD_ENABLE(i), ~MC_RD_ENABLE_MASK);

drivers/gpu/drm/radeon/cypress_dpm.c

140

WREG32_P(SCLK_PWRMGT_CNTL, DYN_LIGHT_SLEEP_EN, ~DYN_LIGHT_SLEEP_EN);

drivers/gpu/drm/radeon/cypress_dpm.c

142

WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);

drivers/gpu/drm/radeon/cypress_dpm.c

144

WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);

drivers/gpu/drm/radeon/cypress_dpm.c

145

WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);

drivers/gpu/drm/radeon/cypress_dpm.c

146

WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);

drivers/gpu/drm/radeon/cypress_dpm.c

150

WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_LIGHT_SLEEP_EN);

drivers/gpu/drm/radeon/cypress_dpm.c

197

WREG32_P(MC_CITF_MISC_RD_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);

drivers/gpu/drm/radeon/cypress_dpm.c

198

WREG32_P(MC_CITF_MISC_WR_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);

drivers/gpu/drm/radeon/cypress_dpm.c

199

WREG32_P(MC_CITF_MISC_VM_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);

drivers/gpu/drm/radeon/cypress_dpm.c

200

WREG32_P(MC_HUB_MISC_HUB_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);

drivers/gpu/drm/radeon/cypress_dpm.c

201

WREG32_P(MC_HUB_MISC_VM_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);

drivers/gpu/drm/radeon/cypress_dpm.c

202

WREG32_P(MC_HUB_MISC_SIP_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);

drivers/gpu/drm/radeon/cypress_dpm.c

203

WREG32_P(MC_XPB_CLK_GAT, MEM_LS_ENABLE, ~MEM_LS_ENABLE);

drivers/gpu/drm/radeon/cypress_dpm.c

204

WREG32_P(VM_L2_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);

drivers/gpu/drm/radeon/cypress_dpm.c

226

WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);

drivers/gpu/drm/radeon/cypress_dpm.c

229

WREG32_P(MPLL_CNTL_MODE, SS_SSEN, ~SS_SSEN);

drivers/gpu/drm/radeon/cypress_dpm.c

231

WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);

drivers/gpu/drm/radeon/cypress_dpm.c

232

WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);

drivers/gpu/drm/radeon/cypress_dpm.c

233

WREG32_P(MPLL_CNTL_MODE, 0, ~SS_SSEN);

drivers/gpu/drm/radeon/cypress_dpm.c

234

WREG32_P(MPLL_CNTL_MODE, 0, ~SS_DSMODE_EN);

drivers/gpu/drm/radeon/cypress_dpm.c

240

WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);

drivers/gpu/drm/radeon/cypress_dpm.c

247

WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);

drivers/gpu/drm/radeon/cypress_dpm.c

249

WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);

drivers/gpu/drm/radeon/cypress_dpm.c

256

WREG32_P(MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF);

drivers/gpu/drm/radeon/cypress_dpm.c

258

WREG32_P(MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF);

drivers/gpu/drm/radeon/cypress_dpm.c

91

WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);

drivers/gpu/drm/radeon/cypress_dpm.c

93

WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);

drivers/gpu/drm/radeon/dce3_1_afmt.c

181

WREG32_P(HDMI0_ACR_32_0 + offset,

drivers/gpu/drm/radeon/dce3_1_afmt.c

184

WREG32_P(HDMI0_ACR_32_1 + offset,

drivers/gpu/drm/radeon/dce3_1_afmt.c

188

WREG32_P(HDMI0_ACR_44_0 + offset,

drivers/gpu/drm/radeon/dce3_1_afmt.c

191

WREG32_P(HDMI0_ACR_44_1 + offset,

drivers/gpu/drm/radeon/dce3_1_afmt.c

195

WREG32_P(HDMI0_ACR_48_0 + offset,

drivers/gpu/drm/radeon/dce3_1_afmt.c

198

WREG32_P(HDMI0_ACR_48_1 + offset,

drivers/gpu/drm/radeon/evergreen.c

1153

WREG32_P(cntl_reg, dividers.post_div, ~(DCLK_DIR_CNTL_EN|DCLK_DIVIDER_MASK));

drivers/gpu/drm/radeon/evergreen.c

1196

WREG32_P(CG_UPLL_FUNC_CNTL_2,

drivers/gpu/drm/radeon/evergreen.c

1201

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);

drivers/gpu/drm/radeon/evergreen.c

1205

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);

drivers/gpu/drm/radeon/evergreen.c

1216

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);

drivers/gpu/drm/radeon/evergreen.c

1219

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);

drivers/gpu/drm/radeon/evergreen.c

1220

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);

drivers/gpu/drm/radeon/evergreen.c

1223

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);

drivers/gpu/drm/radeon/evergreen.c

1232

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);

drivers/gpu/drm/radeon/evergreen.c

1235

WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);

drivers/gpu/drm/radeon/evergreen.c

1238

WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK);

drivers/gpu/drm/radeon/evergreen.c

1241

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);

drivers/gpu/drm/radeon/evergreen.c

1244

WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9);

drivers/gpu/drm/radeon/evergreen.c

1246

WREG32_P(CG_UPLL_FUNC_CNTL_4, UPLL_SPARE_ISPARE9, ~UPLL_SPARE_ISPARE9);

drivers/gpu/drm/radeon/evergreen.c

1249

WREG32_P(CG_UPLL_FUNC_CNTL_2,

drivers/gpu/drm/radeon/evergreen.c

1257

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);

drivers/gpu/drm/radeon/evergreen.c

1262

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);

drivers/gpu/drm/radeon/evergreen.c

1269

WREG32_P(CG_UPLL_FUNC_CNTL_2,

drivers/gpu/drm/radeon/evergreen.c

4855

WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);

drivers/gpu/drm/radeon/evergreen_hdmi.c

224

WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,

drivers/gpu/drm/radeon/kv_smc.c

83

WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);

drivers/gpu/drm/radeon/ni.c

1690

WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA);

drivers/gpu/drm/radeon/ni.c

1697

WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA);

drivers/gpu/drm/radeon/ni.c

2710

WREG32_P(CG_ECLK_CNTL, dividers.post_div, ~(ECLK_DIR_CNTL_EN|ECLK_DIVIDER_MASK));

drivers/gpu/drm/radeon/ni_dpm.c

1021

WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);

drivers/gpu/drm/radeon/ni_dpm.c

1205

WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);

drivers/gpu/drm/radeon/ni_dpm.c

1206

WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);

drivers/gpu/drm/radeon/ni_dpm.c

1207

WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);

drivers/gpu/drm/radeon/ni_dpm.c

1211

WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_SwitchToMinimumPower),

drivers/gpu/drm/radeon/ni_dpm.c

1541

WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK);

drivers/gpu/drm/radeon/ni_dpm.c

1546

WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK);

drivers/gpu/drm/radeon/ni_dpm.c

1551

WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK);

drivers/gpu/drm/radeon/ni_dpm.c

1556

WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK);

drivers/gpu/drm/radeon/ni_dpm.c

1564

WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK);

drivers/gpu/drm/radeon/ni_dpm.c

3503

WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);

drivers/gpu/drm/radeon/ni_dpm.c

3505

WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);

drivers/gpu/drm/radeon/r100.c

2775

WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,

drivers/gpu/drm/radeon/r600.c

209

WREG32_P(CG_UPLL_FUNC_CNTL_2,

drivers/gpu/drm/radeon/r600.c

214

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~(

drivers/gpu/drm/radeon/r600.c

218

WREG32_P(GFX_MACRO_BYPASS_CNTL, UPLL_BYPASS_CNTL,

drivers/gpu/drm/radeon/r600.c

223

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);

drivers/gpu/drm/radeon/r600.c

248

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);

drivers/gpu/drm/radeon/r600.c

252

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REFCLK_SRC_SEL_MASK,

drivers/gpu/drm/radeon/r600.c

256

WREG32_P(CG_UPLL_FUNC_CNTL,

drivers/gpu/drm/radeon/r600.c

260

WREG32_P(CG_UPLL_FUNC_CNTL_2,

drivers/gpu/drm/radeon/r600.c

272

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);

drivers/gpu/drm/radeon/r600.c

277

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);

drivers/gpu/drm/radeon/r600.c

280

WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~UPLL_BYPASS_CNTL);

drivers/gpu/drm/radeon/r600.c

287

WREG32_P(CG_UPLL_FUNC_CNTL_2,

drivers/gpu/drm/radeon/r600_dpm.c

245

WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);

drivers/gpu/drm/radeon/r600_dpm.c

247

WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);

drivers/gpu/drm/radeon/r600_dpm.c

267

WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);

drivers/gpu/drm/radeon/r600_dpm.c

269

WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);

drivers/gpu/drm/radeon/r600_dpm.c

275

WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);

drivers/gpu/drm/radeon/r600_dpm.c

277

WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);

drivers/gpu/drm/radeon/r600_dpm.c

282

WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);

drivers/gpu/drm/radeon/r600_dpm.c

288

WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);

drivers/gpu/drm/radeon/r600_dpm.c

290

WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);

drivers/gpu/drm/radeon/r600_dpm.c

304

WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);

drivers/gpu/drm/radeon/r600_dpm.c

306

WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);

drivers/gpu/drm/radeon/r600_dpm.c

312

WREG32_P(MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF);

drivers/gpu/drm/radeon/r600_dpm.c

314

WREG32_P(MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF);

drivers/gpu/drm/radeon/r600_dpm.c

320

WREG32_P(CG_SPLL_FUNC_CNTL, SPLL_BYPASS_EN, ~SPLL_BYPASS_EN);

drivers/gpu/drm/radeon/r600_dpm.c

322

WREG32_P(CG_SPLL_FUNC_CNTL, 0, ~SPLL_BYPASS_EN);

drivers/gpu/drm/radeon/r600_dpm.c

359

WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);

drivers/gpu/drm/radeon/r600_dpm.c

361

WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);

drivers/gpu/drm/radeon/r600_dpm.c

363

WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);

drivers/gpu/drm/radeon/r600_dpm.c

365

WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);

drivers/gpu/drm/radeon/r600_dpm.c

375

WREG32_P(CG_TPC, TPU(u), ~TPU_MASK);

drivers/gpu/drm/radeon/r600_dpm.c

380

WREG32_P(CG_TPC, TPCC(c), ~TPCC_MASK);

drivers/gpu/drm/radeon/r600_dpm.c

385

WREG32_P(CG_SSP, CG_SSTU(u), ~CG_SSTU_MASK);

drivers/gpu/drm/radeon/r600_dpm.c

390

WREG32_P(CG_SSP, CG_SST(t), ~CG_SST_MASK);

drivers/gpu/drm/radeon/r600_dpm.c

395

WREG32_P(CG_GIT, CG_GICST(t), ~CG_GICST_MASK);

drivers/gpu/drm/radeon/r600_dpm.c

400

WREG32_P(CG_FC_T, FC_TU(u), ~FC_TU_MASK);

drivers/gpu/drm/radeon/r600_dpm.c

405

WREG32_P(CG_FC_T, FC_T(t), ~FC_T_MASK);

drivers/gpu/drm/radeon/r600_dpm.c

410

WREG32_P(CG_CTX_CGTT3D_R, PHC(p), ~PHC_MASK);

drivers/gpu/drm/radeon/r600_dpm.c

415

WREG32_P(CG_CTX_CGTT3D_R, SDC(s), ~SDC_MASK);

drivers/gpu/drm/radeon/r600_dpm.c

420

WREG32_P(CG_VDDC3D_OOR, SU(u), ~SU_MASK);

drivers/gpu/drm/radeon/r600_dpm.c

425

WREG32_P(CG_VDDC3D_OOR, PHC(p), ~PHC_MASK);

drivers/gpu/drm/radeon/r600_dpm.c

430

WREG32_P(CG_VDDC3D_OOR, SDC(s), ~SDC_MASK);

drivers/gpu/drm/radeon/r600_dpm.c

435

WREG32_P(MPLL_TIME, MPLL_LOCK_TIME(lock_time), ~MPLL_LOCK_TIME_MASK);

drivers/gpu/drm/radeon/r600_dpm.c

440

WREG32_P(MPLL_TIME, MPLL_RESET_TIME(reset_time), ~MPLL_RESET_TIME_MASK);

drivers/gpu/drm/radeon/r600_dpm.c

447

WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),

drivers/gpu/drm/radeon/r600_dpm.c

450

WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),

drivers/gpu/drm/radeon/r600_dpm.c

458

WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),

drivers/gpu/drm/radeon/r600_dpm.c

461

WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),

drivers/gpu/drm/radeon/r600_dpm.c

469

WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),

drivers/gpu/drm/radeon/r600_dpm.c

472

WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),

drivers/gpu/drm/radeon/r600_dpm.c

479

WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2),

drivers/gpu/drm/radeon/r600_dpm.c

486

WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2),

drivers/gpu/drm/radeon/r600_dpm.c

493

WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2),

drivers/gpu/drm/radeon/r600_dpm.c

500

WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2),

drivers/gpu/drm/radeon/r600_dpm.c

506

WREG32_P(VID_RT, SSTU(u), ~SSTU_MASK);

drivers/gpu/drm/radeon/r600_dpm.c

511

WREG32_P(VID_RT, VID_CRTU(u), ~VID_CRTU_MASK);

drivers/gpu/drm/radeon/r600_dpm.c

516

WREG32_P(VID_RT, VID_CRT(rt), ~VID_CRT_MASK);

drivers/gpu/drm/radeon/r600_dpm.c

565

WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), CTXSW_FREQ_STATE_ENABLE,

drivers/gpu/drm/radeon/r600_dpm.c

568

WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), 0,

drivers/gpu/drm/radeon/r600_dpm.c

577

WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4),

drivers/gpu/drm/radeon/r600_dpm.c

586

WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4),

drivers/gpu/drm/radeon/r600_dpm.c

595

WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4),

drivers/gpu/drm/radeon/r600_dpm.c

608

WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), tmp, ~CTXSW_FREQ_DISPLAY_WATERMARK);

drivers/gpu/drm/radeon/r600_dpm.c

619

WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), tmp, ~CTXSW_FREQ_GEN2PCIE_VOLT);

drivers/gpu/drm/radeon/r600_dpm.c

643

WREG32_P(TARGET_AND_CURRENT_PROFILE_INDEX, DYN_PWR_ENTER_INDEX(index),

drivers/gpu/drm/radeon/r600_dpm.c

752

WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);

drivers/gpu/drm/radeon/r600_dpm.c

753

WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);

drivers/gpu/drm/radeon/r600_dpm.c

754

WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);

drivers/gpu/drm/radeon/r600_hdmi.c

187

WREG32_P(acr_ctl + offset,

drivers/gpu/drm/radeon/r600_hdmi.c

193

WREG32_P(HDMI0_ACR_32_0 + offset,

drivers/gpu/drm/radeon/r600_hdmi.c

196

WREG32_P(HDMI0_ACR_32_1 + offset,

drivers/gpu/drm/radeon/r600_hdmi.c

200

WREG32_P(HDMI0_ACR_44_0 + offset,

drivers/gpu/drm/radeon/r600_hdmi.c

203

WREG32_P(HDMI0_ACR_44_1 + offset,

drivers/gpu/drm/radeon/r600_hdmi.c

207

WREG32_P(HDMI0_ACR_48_0 + offset,

drivers/gpu/drm/radeon/r600_hdmi.c

210

WREG32_P(HDMI0_ACR_48_1 + offset,

drivers/gpu/drm/radeon/r600_hdmi.c

335

WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,

drivers/gpu/drm/radeon/r600_hdmi.c

349

WREG32_P(HDMI0_INFOFRAME_CONTROL1 + offset,

drivers/gpu/drm/radeon/r600_hdmi.c

362

WREG32_P(HDMI0_60958_0 + offset,

drivers/gpu/drm/radeon/r600_hdmi.c

367

WREG32_P(HDMI0_60958_1 + offset,

drivers/gpu/drm/radeon/radeon.h

2542

#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)

drivers/gpu/drm/radeon/radeon.h

2543

#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))

drivers/gpu/drm/radeon/radeon_cursor.c

138

WREG32_P(RADEON_MM_DATA, (RADEON_CRTC_CUR_EN |

drivers/gpu/drm/radeon/radeon_display.c

85

WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

331

WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask));

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

333

WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

335

WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl));

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

347

WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask));

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

349

WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

351

WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~(mask | crtc_ext_cntl));

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

927

WREG32_P(RADEON_CLOCK_CNTL_INDEX,

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

948

WREG32_P(RADEON_CLOCK_CNTL_INDEX,

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1279

WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1316

WREG32_P(RADEON_GPIOPAD_A, 0, ~1);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1366

WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1607

WREG32_P(RADEON_GPIOPAD_A, 1, ~1);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1663

WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

615

WREG32_P(RADEON_DAC_CNTL,

drivers/gpu/drm/radeon/radeon_uvd.c

1017

WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);

drivers/gpu/drm/radeon/radeon_uvd.c

1022

WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);

drivers/gpu/drm/radeon/radeon_uvd.c

1033

WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);

drivers/gpu/drm/radeon/rs780_dpm.c

1063

WREG32_P(FVTHROT_FBDIV_REG1, 0, ~FORCE_FEEDBACK_DIV);

drivers/gpu/drm/radeon/rs780_dpm.c

202

WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1, RANGE_SLOW_CLK_FEEDBACK_DIV_EN,

drivers/gpu/drm/radeon/rs780_dpm.c

205

WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1,

drivers/gpu/drm/radeon/rs780_dpm.c

214

WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fbdiv),

drivers/gpu/drm/radeon/rs780_dpm.c

217

WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fbdiv),

drivers/gpu/drm/radeon/rs780_dpm.c

220

WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV);

drivers/gpu/drm/radeon/rs780_dpm.c

260

WREG32_P(FVTHROT_PWM_CTRL_REG0,

drivers/gpu/drm/radeon/rs780_dpm.c

264

WREG32_P(FVTHROT_PWM_CTRL_REG0,

drivers/gpu/drm/radeon/rs780_dpm.c

268

WREG32_P(FVTHROT_PWM_CTRL_REG0, FORCE_STARTING_PWM_HIGHTIME,

drivers/gpu/drm/radeon/rs780_dpm.c

272

WREG32_P(FVTHROT_PWM_CTRL_REG0, INVERT_PWM_WAVEFORM, ~INVERT_PWM_WAVEFORM);

drivers/gpu/drm/radeon/rs780_dpm.c

274

WREG32_P(FVTHROT_PWM_CTRL_REG0, 0, ~INVERT_PWM_WAVEFORM);

drivers/gpu/drm/radeon/rs780_dpm.c

287

WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1,

drivers/gpu/drm/radeon/rs780_dpm.c

306

WREG32_P(FVTHROT_CNTRL_REG, ENABLE_FV_THROT | ENABLE_FV_UPDATE,

drivers/gpu/drm/radeon/rs780_dpm.c

309

WREG32_P(FVTHROT_CNTRL_REG, 0,

drivers/gpu/drm/radeon/rs780_dpm.c

316

WREG32_P(FVTHROT_CNTRL_REG, ENABLE_FV_THROT_IO, ~ENABLE_FV_THROT_IO);

drivers/gpu/drm/radeon/rs780_dpm.c

318

WREG32_P(FVTHROT_CNTRL_REG, 0, ~ENABLE_FV_THROT_IO);

drivers/gpu/drm/radeon/rs780_dpm.c

338

WREG32_P(FVTHROT_FBDIV_REG2,

drivers/gpu/drm/radeon/rs780_dpm.c

342

WREG32_P(FVTHROT_CNTRL_REG,

drivers/gpu/drm/radeon/rs780_dpm.c

349

WREG32_P(FVTHROT_CNTRL_REG, 0, ~(FORCE_TREND_SEL | TREND_SEL_MODE));

drivers/gpu/drm/radeon/rs780_dpm.c

359

WREG32_P(FVTHROT_FBDIV_REG1, MAX_FEEDBACK_STEP(1), ~MAX_FEEDBACK_STEP_MASK);

drivers/gpu/drm/radeon/rs780_dpm.c

375

WREG32_P(CG_INTGFX_MISC, 0, ~0xFFF00000);

drivers/gpu/drm/radeon/rs780_dpm.c

386

WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);

drivers/gpu/drm/radeon/rs780_dpm.c

390

WREG32_P(FVTHROT_PWM_CTRL_REG0,

drivers/gpu/drm/radeon/rs780_dpm.c

394

WREG32_P(FVTHROT_PWM_CTRL_REG0,

drivers/gpu/drm/radeon/rs780_dpm.c

397

WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1, 0,

drivers/gpu/drm/radeon/rs780_dpm.c

402

WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);

drivers/gpu/drm/radeon/rs780_dpm.c

412

WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);

drivers/gpu/drm/radeon/rs780_dpm.c

414

WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fb_div),

drivers/gpu/drm/radeon/rs780_dpm.c

416

WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fb_div),

drivers/gpu/drm/radeon/rs780_dpm.c

418

WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV);

drivers/gpu/drm/radeon/rs780_dpm.c

422

WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);

drivers/gpu/drm/radeon/rs780_dpm.c

462

WREG32_P(FVTHROT_FBDIV_REG0,

drivers/gpu/drm/radeon/rs780_dpm.c

467

WREG32_P(FVTHROT_FBDIV_REG1, 0, ~FORCE_FEEDBACK_DIV);

drivers/gpu/drm/radeon/rs780_dpm.c

486

WREG32_P(CG_INTGFX_MISC, 0, ~FVTHROT_VBLANK_SEL);

drivers/gpu/drm/radeon/rs780_dpm.c

488

WREG32_P(CG_INTGFX_MISC, FVTHROT_VBLANK_SEL, ~FVTHROT_VBLANK_SEL);

drivers/gpu/drm/radeon/rs780_dpm.c

540

WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);

drivers/gpu/drm/radeon/rs780_dpm.c

544

WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1,

drivers/gpu/drm/radeon/rs780_dpm.c

547

WREG32_P(FVTHROT_PWM_CTRL_REG0, 0, ~FORCE_STARTING_PWM_HIGHTIME);

drivers/gpu/drm/radeon/rs780_dpm.c

550

WREG32_P(FVTHROT_PWM_CTRL_REG0,

drivers/gpu/drm/radeon/rs780_dpm.c

554

WREG32_P(FVTHROT_PWM_CTRL_REG0,

drivers/gpu/drm/radeon/rs780_dpm.c

560

WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);

drivers/gpu/drm/radeon/rv6xx_dpm.c

1173

WREG32_P(GENERAL_PWRMGT, BACKBIAS_PAD_EN | BACKBIAS_DPM_CNTL,

drivers/gpu/drm/radeon/rv6xx_dpm.c

1176

WREG32_P(GENERAL_PWRMGT, 0,

drivers/gpu/drm/radeon/rv6xx_dpm.c

1212

WREG32_P(GENERAL_PWRMGT, SW_GPIO_INDEX(R600_POWER_LEVEL_CTXSW),

drivers/gpu/drm/radeon/rv6xx_dpm.c

1224

WREG32_P(GENERAL_PWRMGT, SW_GPIO_INDEX(R600_POWER_LEVEL_CTXSW),

drivers/gpu/drm/radeon/rv6xx_dpm.c

1237

WREG32_P(GENERAL_PWRMGT, BACKBIAS_VALUE, ~BACKBIAS_VALUE);

drivers/gpu/drm/radeon/rv6xx_dpm.c

1239

WREG32_P(GENERAL_PWRMGT, 0, ~BACKBIAS_VALUE);

drivers/gpu/drm/radeon/rv6xx_dpm.c

1258

WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);

drivers/gpu/drm/radeon/rv6xx_dpm.c

1260

WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);

drivers/gpu/drm/radeon/rv6xx_dpm.c

1267

WREG32_P(GENERAL_PWRMGT, BACKBIAS_DPM_CNTL, ~BACKBIAS_DPM_CNTL);

drivers/gpu/drm/radeon/rv6xx_dpm.c

1269

WREG32_P(GENERAL_PWRMGT, 0, ~BACKBIAS_DPM_CNTL);

drivers/gpu/drm/radeon/rv6xx_dpm.c

1380

WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);

drivers/gpu/drm/radeon/rv6xx_dpm.c

1382

WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);

drivers/gpu/drm/radeon/rv6xx_dpm.c

1384

WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);

drivers/gpu/drm/radeon/rv6xx_dpm.c

1488

WREG32_P(DCE3_LVTMA_DATA_SYNCHRONIZATION, LVTMA_PFREQCHG, ~LVTMA_PFREQCHG);

drivers/gpu/drm/radeon/rv6xx_dpm.c

1490

WREG32_P(LVTMA_DATA_SYNCHRONIZATION, LVTMA_PFREQCHG, ~LVTMA_PFREQCHG);

drivers/gpu/drm/radeon/rv6xx_dpm.c

317

WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),

drivers/gpu/drm/radeon/rv6xx_dpm.c

324

WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),

drivers/gpu/drm/radeon/rv6xx_dpm.c

332

WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),

drivers/gpu/drm/radeon/rv6xx_dpm.c

335

WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),

drivers/gpu/drm/radeon/rv6xx_dpm.c

342

WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKS(clk_s), ~CLKS_MASK);

drivers/gpu/drm/radeon/rv6xx_dpm.c

348

WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKV(clk_v), ~CLKV_MASK);

drivers/gpu/drm/radeon/rv6xx_dpm.c

355

WREG32_P(CG_MPLL_SPREAD_SPECTRUM, SSEN, ~SSEN);

drivers/gpu/drm/radeon/rv6xx_dpm.c

357

WREG32_P(CG_MPLL_SPREAD_SPECTRUM, 0, ~SSEN);

drivers/gpu/drm/radeon/rv6xx_dpm.c

364

WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);

drivers/gpu/drm/radeon/rv6xx_dpm.c

366

WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);

drivers/gpu/drm/radeon/rv6xx_dpm.c

373

WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4),

drivers/gpu/drm/radeon/rv6xx_dpm.c

376

WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), 0, ~LEVEL0_MPLL_DIV_EN);

drivers/gpu/drm/radeon/rv6xx_dpm.c

382

WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4),

drivers/gpu/drm/radeon/rv6xx_dpm.c

389

WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), LEVEL0_MPLL_FB_DIV(divider),

drivers/gpu/drm/radeon/rv6xx_dpm.c

396

WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4),

drivers/gpu/drm/radeon/rv6xx_dpm.c

402

WREG32_P(VID_RT, BRT(rt), ~BRT_MASK);

drivers/gpu/drm/radeon/rv6xx_dpm.c

407

WREG32_P(SPLL_CNTL_MODE, SPLL_DIV_SYNC, ~SPLL_DIV_SYNC);

drivers/gpu/drm/radeon/rv6xx_dpm.c

734

WREG32_P(VID_UPPER_GPIO_CNTL, MEDIUM_BACKBIAS_VALUE, ~MEDIUM_BACKBIAS_VALUE);

drivers/gpu/drm/radeon/rv6xx_dpm.c

736

WREG32_P(VID_UPPER_GPIO_CNTL, 0, ~MEDIUM_BACKBIAS_VALUE);

drivers/gpu/drm/radeon/rv6xx_dpm.c

739

WREG32_P(VID_UPPER_GPIO_CNTL, HIGH_BACKBIAS_VALUE, ~HIGH_BACKBIAS_VALUE);

drivers/gpu/drm/radeon/rv6xx_dpm.c

741

WREG32_P(VID_UPPER_GPIO_CNTL, 0, ~HIGH_BACKBIAS_VALUE);

drivers/gpu/drm/radeon/rv6xx_dpm.c

776

WREG32_P(VID_UPPER_GPIO_CNTL, LOW_BACKBIAS_VALUE, ~LOW_BACKBIAS_VALUE);

drivers/gpu/drm/radeon/rv6xx_dpm.c

778

WREG32_P(VID_UPPER_GPIO_CNTL, 0, ~LOW_BACKBIAS_VALUE);

drivers/gpu/drm/radeon/rv6xx_dpm.c

991

WREG32_P(MCLK_PWRMGT_CNTL, USE_DISPLAY_GAP, ~USE_DISPLAY_GAP);

drivers/gpu/drm/radeon/rv6xx_dpm.c

993

WREG32_P(MCLK_PWRMGT_CNTL, 0, ~USE_DISPLAY_GAP);

drivers/gpu/drm/radeon/rv730_dpm.c

450

WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);

drivers/gpu/drm/radeon/rv730_dpm.c

452

WREG32_P(TCI_MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF);

drivers/gpu/drm/radeon/rv730_dpm.c

454

WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);

drivers/gpu/drm/radeon/rv730_dpm.c

466

WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);

drivers/gpu/drm/radeon/rv730_dpm.c

468

WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);

drivers/gpu/drm/radeon/rv730_dpm.c

470

WREG32_P(TCI_MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF);

drivers/gpu/drm/radeon/rv740_dpm.c

403

WREG32_P(MPLL_CNTL_MODE, SS_SSEN, ~SS_SSEN);

drivers/gpu/drm/radeon/rv740_dpm.c

405

WREG32_P(MPLL_CNTL_MODE, 0, ~SS_SSEN);

drivers/gpu/drm/radeon/rv770.c

102

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REF_DIV(1), ~UPLL_REF_DIV_MASK);

drivers/gpu/drm/radeon/rv770.c

103

WREG32_P(CG_UPLL_FUNC_CNTL_2,

drivers/gpu/drm/radeon/rv770.c

110

WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div),

drivers/gpu/drm/radeon/rv770.c

117

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);

drivers/gpu/drm/radeon/rv770.c

122

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);

drivers/gpu/drm/radeon/rv770.c

123

WREG32_P(CG_UPLL_FUNC_CNTL_3, 0, ~UPLL_FB_DIV(1));

drivers/gpu/drm/radeon/rv770.c

130

WREG32_P(CG_UPLL_FUNC_CNTL_2,

drivers/gpu/drm/radeon/rv770.c

64

WREG32_P(CG_UPLL_FUNC_CNTL_2,

drivers/gpu/drm/radeon/rv770.c

70

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);

drivers/gpu/drm/radeon/rv770.c

85

WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK);

drivers/gpu/drm/radeon/rv770.c

88

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK));

drivers/gpu/drm/radeon/rv770.c

91

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);

drivers/gpu/drm/radeon/rv770.c

92

WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(1), ~UPLL_FB_DIV(1));

drivers/gpu/drm/radeon/rv770.c

99

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);

drivers/gpu/drm/radeon/rv770_dpm.c

1338

WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);

drivers/gpu/drm/radeon/rv770_dpm.c

1340

WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);

drivers/gpu/drm/radeon/rv770_dpm.c

135

WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);

drivers/gpu/drm/radeon/rv770_dpm.c

1367

WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);

drivers/gpu/drm/radeon/rv770_dpm.c

1369

WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);

drivers/gpu/drm/radeon/rv770_dpm.c

137

WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);

drivers/gpu/drm/radeon/rv770_dpm.c

138

WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);

drivers/gpu/drm/radeon/rv770_dpm.c

139

WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);

drivers/gpu/drm/radeon/rv770_dpm.c

1588

WREG32_P(GENERAL_PWRMGT, SW_SMIO_INDEX(0), ~SW_SMIO_INDEX_MASK);

drivers/gpu/drm/radeon/rv770_dpm.c

1634

WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);

drivers/gpu/drm/radeon/rv770_dpm.c

1635

WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);

drivers/gpu/drm/radeon/rv770_dpm.c

1636

WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);

drivers/gpu/drm/radeon/rv770_dpm.c

1640

WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_SwitchToMinimumPower),

drivers/gpu/drm/radeon/rv770_dpm.c

1653

WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_ResumeFromMinimumPower),

drivers/gpu/drm/radeon/rv770_dpm.c

1665

WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);

drivers/gpu/drm/radeon/rv770_dpm.c

178

WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);

drivers/gpu/drm/radeon/rv770_dpm.c

183

WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);

drivers/gpu/drm/radeon/rv770_dpm.c

1843

WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);

drivers/gpu/drm/radeon/rv770_dpm.c

1845

WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);

drivers/gpu/drm/radeon/rv770_dpm.c

1847

WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);

drivers/gpu/drm/radeon/rv770_dpm.c

185

WREG32_P(MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF);

drivers/gpu/drm/radeon/rv770_dpm.c

187

WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);

drivers/gpu/drm/radeon/rv770_dpm.c

1885

WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);

drivers/gpu/drm/radeon/rv770_dpm.c

1886

WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);

drivers/gpu/drm/radeon/rv770_dpm.c

1887

WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);

drivers/gpu/drm/radeon/rv770_dpm.c

199

WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);

drivers/gpu/drm/radeon/rv770_dpm.c

201

WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);

drivers/gpu/drm/radeon/rv770_dpm.c

203

WREG32_P(MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF);

drivers/gpu/drm/radeon/rv770_dpm.c

218

WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);

drivers/gpu/drm/radeon/rv770_dpm.c

220

WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);

drivers/gpu/drm/radeon/rv770_dpm.c

225

WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);

drivers/gpu/drm/radeon/rv770_dpm.c

776

WREG32_P(GENERAL_PWRMGT, BACKBIAS_PAD_EN, ~BACKBIAS_PAD_EN);

drivers/gpu/drm/radeon/rv770_dpm.c

778

WREG32_P(GENERAL_PWRMGT, 0, ~(BACKBIAS_VALUE | BACKBIAS_PAD_EN));

drivers/gpu/drm/radeon/rv770_dpm.c

788

WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);

drivers/gpu/drm/radeon/rv770_dpm.c

795

WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);

drivers/gpu/drm/radeon/rv770_dpm.c

797

WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);

drivers/gpu/drm/radeon/rv770_dpm.c

799

WREG32_P(CG_MPLL_SPREAD_SPECTRUM, 0, ~SSEN);

drivers/gpu/drm/radeon/rv770_dpm.c

843

WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);

drivers/gpu/drm/radeon/rv770_dpm.c

855

WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);

drivers/gpu/drm/radeon/rv770_dpm.c

857

WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);

drivers/gpu/drm/radeon/rv770_dpm.c

859

WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);

drivers/gpu/drm/radeon/rv770_dpm.c

861

WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);

drivers/gpu/drm/radeon/rv770_dpm.c

876

WREG32_P(SPLL_CNTL_MODE, SPLL_DIV_SYNC, ~SPLL_DIV_SYNC);

drivers/gpu/drm/radeon/rv770_smc.c

382

WREG32_P(SMC_IO, SMC_RST_N, ~SMC_RST_N);

drivers/gpu/drm/radeon/rv770_smc.c

387

WREG32_P(SMC_IO, 0, ~SMC_RST_N);

drivers/gpu/drm/radeon/rv770_smc.c

392

WREG32_P(SMC_IO, 0, ~SMC_CLK_EN);

drivers/gpu/drm/radeon/rv770_smc.c

397

WREG32_P(SMC_IO, SMC_CLK_EN, ~SMC_CLK_EN);

drivers/gpu/drm/radeon/rv770_smc.c

421

WREG32_P(SMC_MSG, HOST_SMC_MSG(msg), ~HOST_SMC_MSG_MASK);

drivers/gpu/drm/radeon/si.c

6355

WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);

drivers/gpu/drm/radeon/si.c

6981

WREG32_P(CG_UPLL_FUNC_CNTL_2,

drivers/gpu/drm/radeon/si.c

6986

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);

drivers/gpu/drm/radeon/si.c

7000

WREG32_P(CG_UPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK);

drivers/gpu/drm/radeon/si.c

7003

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);

drivers/gpu/drm/radeon/si.c

7006

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);

drivers/gpu/drm/radeon/si.c

7009

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);

drivers/gpu/drm/radeon/si.c

7018

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);

drivers/gpu/drm/radeon/si.c

7021

WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);

drivers/gpu/drm/radeon/si.c

7024

WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK);

drivers/gpu/drm/radeon/si.c

7027

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);

drivers/gpu/drm/radeon/si.c

7030

WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9);

drivers/gpu/drm/radeon/si.c

7032

WREG32_P(CG_UPLL_FUNC_CNTL_4, UPLL_SPARE_ISPARE9, ~UPLL_SPARE_ISPARE9);

drivers/gpu/drm/radeon/si.c

7035

WREG32_P(CG_UPLL_FUNC_CNTL_2,

drivers/gpu/drm/radeon/si.c

7043

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);

drivers/gpu/drm/radeon/si.c

7048

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);

drivers/gpu/drm/radeon/si.c

7055

WREG32_P(CG_UPLL_FUNC_CNTL_2,

drivers/gpu/drm/radeon/si_dpm.c

3249

WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);

drivers/gpu/drm/radeon/si_dpm.c

3251

WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);

drivers/gpu/drm/radeon/si_dpm.c

3253

WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);

drivers/gpu/drm/radeon/si_dpm.c

3278

WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);

drivers/gpu/drm/radeon/si_dpm.c

3283

WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);

drivers/gpu/drm/radeon/si_dpm.c

3289

WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);

drivers/gpu/drm/radeon/si_dpm.c

3291

WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);

drivers/gpu/drm/radeon/si_dpm.c

3536

WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);

drivers/gpu/drm/radeon/si_dpm.c

3538

WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);

drivers/gpu/drm/radeon/si_dpm.c

3543

WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);

drivers/gpu/drm/radeon/si_dpm.c

3618

WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);

drivers/gpu/drm/radeon/si_dpm.c

3619

WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,

drivers/gpu/drm/radeon/si_dpm.c

3675

WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);

drivers/gpu/drm/radeon/si_dpm.c

3677

WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);

drivers/gpu/drm/radeon/si_dpm.c

3678

WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);

drivers/gpu/drm/radeon/si_dpm.c

3708

WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);

drivers/gpu/drm/radeon/si_dpm.c

3720

WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);

drivers/gpu/drm/radeon/si_dpm.c

3722

WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);

drivers/gpu/drm/radeon/si_dpm.c

3725

WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);

drivers/gpu/drm/radeon/si_dpm.c

3728

WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);

drivers/gpu/drm/radeon/si_dpm.c

5657

WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);

drivers/gpu/drm/radeon/si_dpm.c

5659

WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);

drivers/gpu/drm/radeon/si_dpm.c

5941

WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);

drivers/gpu/drm/radeon/si_dpm.c

5942

WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);

drivers/gpu/drm/radeon/si_dpm.c

5943

WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);

drivers/gpu/drm/radeon/si_smc.c

266

WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0);

drivers/gpu/drm/radeon/si_smc.c

276

WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);

drivers/gpu/drm/radeon/si_smc.c

42

WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);

drivers/gpu/drm/radeon/sumo_dpm.c

1169

WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(49 + (high_temp / 1000)), ~DIG_THERM_INTH_MASK);

drivers/gpu/drm/radeon/sumo_dpm.c

1170

WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(49 + (low_temp / 1000)), ~DIG_THERM_INTL_MASK);

drivers/gpu/drm/radeon/sumo_dpm.c

126

WREG32_P(CG_GIT, CG_GICST(p), ~CG_GICST_MASK);

drivers/gpu/drm/radeon/sumo_dpm.c

173

WREG32_P(CG_PWR_GATING_CNTL, PGP(p) | PGU(u),

drivers/gpu/drm/radeon/sumo_dpm.c

179

WREG32_P(CG_CG_VOLTAGE_CNTL, PGP(p) | PGU(u),

drivers/gpu/drm/radeon/sumo_dpm.c

275

WREG32_P(CG_PWR_GATING_CNTL, DYN_PWR_DOWN_EN, ~DYN_PWR_DOWN_EN);

drivers/gpu/drm/radeon/sumo_dpm.c

277

WREG32_P(CG_PWR_GATING_CNTL, 0, ~DYN_PWR_DOWN_EN);

drivers/gpu/drm/radeon/sumo_dpm.c

434

WREG32_P(CG_FFCT_0 + (i * 4), UTC_0(sumo_utc[i]), ~UTC_0_MASK);

drivers/gpu/drm/radeon/sumo_dpm.c

435

WREG32_P(CG_FFCT_0 + (i * 4), DTC_0(sumo_dtc[i]), ~DTC_0_MASK);

drivers/gpu/drm/radeon/sumo_dpm.c

439

WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);

drivers/gpu/drm/radeon/sumo_dpm.c

441

WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);

drivers/gpu/drm/radeon/sumo_dpm.c

444

WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);

drivers/gpu/drm/radeon/sumo_dpm.c

447

WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);

drivers/gpu/drm/radeon/sumo_dpm.c

478

WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),

drivers/gpu/drm/radeon/sumo_dpm.c

481

WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),

drivers/gpu/drm/radeon/sumo_dpm.c

484

WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),

drivers/gpu/drm/radeon/sumo_dpm.c

487

WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),

drivers/gpu/drm/radeon/sumo_dpm.c

563

WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS);

drivers/gpu/drm/radeon/sumo_dpm.c

569

WREG32_P(DEEP_SLEEP_CNTL, ENABLE_DS, ~ENABLE_DS);

drivers/gpu/drm/radeon/sumo_dpm.c

584

WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),

drivers/gpu/drm/radeon/sumo_dpm.c

587

WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),

drivers/gpu/drm/radeon/sumo_dpm.c

590

WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),

drivers/gpu/drm/radeon/sumo_dpm.c

593

WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),

drivers/gpu/drm/radeon/sumo_dpm.c

607

WREG32_P(CG_SCLK_DPM_CTRL_3, DPM_SCLK_ENABLE, ~DPM_SCLK_ENABLE);

drivers/gpu/drm/radeon/sumo_dpm.c

612

WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~DPM_SCLK_ENABLE);

drivers/gpu/drm/radeon/sumo_dpm.c

618

WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE_EN, ~FORCE_SCLK_STATE_EN);

drivers/gpu/drm/radeon/sumo_dpm.c

620

WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_SCLK_STATE_EN);

drivers/gpu/drm/radeon/sumo_dpm.c

726

WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE(index), ~FORCE_SCLK_STATE_MASK);

drivers/gpu/drm/radeon/sumo_dpm.c

773

WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);

drivers/gpu/drm/radeon/sumo_dpm.c

778

WREG32_P(CG_SCLK_DPM_CTRL_5, SCLK_FSTATE_BOOTUP(0), ~SCLK_FSTATE_BOOTUP_MASK);

drivers/gpu/drm/radeon/sumo_dpm.c

793

WREG32_P(CG_ACPI_CNTL, SCLK_ACPI_DIV(dividers.post_div), ~SCLK_ACPI_DIV_MASK);

drivers/gpu/drm/radeon/sumo_dpm.c

794

WREG32_P(CG_ACPI_VOLTAGE_CNTL, 0, ~ACPI_VOLTAGE_EN);

drivers/gpu/drm/radeon/sumo_dpm.c

89

WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);

drivers/gpu/drm/radeon/sumo_dpm.c

904

WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS);

drivers/gpu/drm/radeon/sumo_dpm.c

909

WREG32_P(CG_AT_0, CG_R(0xffff), ~CG_R_MASK);

drivers/gpu/drm/radeon/sumo_dpm.c

91

WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);

drivers/gpu/drm/radeon/sumo_dpm.c

910

WREG32_P(CG_AT_0, CG_L(0), ~CG_L_MASK);

drivers/gpu/drm/radeon/sumo_dpm.c

915

WREG32_P(SCLK_PWRMGT_CNTL, FIR_RESET, ~FIR_RESET);

drivers/gpu/drm/radeon/sumo_dpm.c

92

WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);

drivers/gpu/drm/radeon/sumo_dpm.c

920

WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_RESET);

drivers/gpu/drm/radeon/sumo_dpm.c

93

WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);

drivers/gpu/drm/radeon/sumo_dpm.c

953

WREG32_P(CG_DPM_VOLTAGE_CNTL, DPM_VOLTAGE_EN, ~DPM_VOLTAGE_EN);

drivers/gpu/drm/radeon/sumo_dpm.c

954

WREG32_P(CG_CG_VOLTAGE_CNTL, 0, ~CG_VOLTAGE_EN);

drivers/gpu/drm/radeon/sumo_dpm.c

956

WREG32_P(CG_CG_VOLTAGE_CNTL, CG_VOLTAGE_EN, ~CG_VOLTAGE_EN);

drivers/gpu/drm/radeon/sumo_dpm.c

957

WREG32_P(CG_DPM_VOLTAGE_CNTL, 0, ~DPM_VOLTAGE_EN);

drivers/gpu/drm/radeon/sumo_dpm.c

963

WREG32_P(CG_SCLK_DPM_CTRL_3, CNB_THERMTHRO_MASK_SCLK,

drivers/gpu/drm/radeon/sumo_dpm.c

990

WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_NB_PSTATE_1, ~FORCE_NB_PSTATE_1);

drivers/gpu/drm/radeon/sumo_dpm.c

992

WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_NB_PSTATE_1);

drivers/gpu/drm/radeon/trinity_dpm.c

1010

WREG32_P(CG_THERMAL_INT_CTRL, DIG_THERM_INTH(49 + (high_temp / 1000)), ~DIG_THERM_INTH_MASK);

drivers/gpu/drm/radeon/trinity_dpm.c

1011

WREG32_P(CG_THERMAL_INT_CTRL, DIG_THERM_INTL(49 + (low_temp / 1000)), ~DIG_THERM_INTL_MASK);

drivers/gpu/drm/radeon/trinity_dpm.c

341

WREG32_P(CG_GIPOTS, CG_GIPOT(p), ~CG_GIPOT_MASK);

drivers/gpu/drm/radeon/trinity_dpm.c

398

WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);

drivers/gpu/drm/radeon/trinity_dpm.c

400

WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);

drivers/gpu/drm/radeon/trinity_dpm.c

401

WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);

drivers/gpu/drm/radeon/trinity_dpm.c

402

WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);

drivers/gpu/drm/radeon/trinity_dpm.c

413

WREG32_P(seq[i], seq[i+1], ~seq[i+2]);

drivers/gpu/drm/radeon/trinity_dpm.c

461

WREG32_P(SCLK_PWRMGT_CNTL, DYN_PWR_DOWN_EN, ~DYN_PWR_DOWN_EN);

drivers/gpu/drm/radeon/trinity_dpm.c

463

WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_PWR_DOWN_EN);

drivers/gpu/drm/radeon/trinity_dpm.c

714

WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);

drivers/gpu/drm/radeon/trinity_dpm.c

715

WREG32_P(CG_CG_VOLTAGE_CNTL, 0, ~EN);

drivers/gpu/drm/radeon/trinity_dpm.c

745

WREG32_P(CG_CG_VOLTAGE_CNTL, EN, ~EN);

drivers/gpu/drm/radeon/trinity_dpm.c

756

WREG32_P(SCLK_PWRMGT_CNTL, 0, ~(RESET_SCLK_CNT | RESET_BUSY_CNT));

drivers/gpu/drm/radeon/trinity_dpm.c

761

WREG32_P(SCLK_PWRMGT_CNTL, RESET_SCLK_CNT | RESET_BUSY_CNT,

drivers/gpu/drm/radeon/uvd_v1_0.c

227

WREG32_P(UVD_VCPU_CNTL, 0x10, ~0x10);

drivers/gpu/drm/radeon/uvd_v1_0.c

277

WREG32_P(UVD_MASTINT_EN, 0, ~(1 << 1));

drivers/gpu/drm/radeon/uvd_v1_0.c

280

WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8));

drivers/gpu/drm/radeon/uvd_v1_0.c

281

WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3));

drivers/gpu/drm/radeon/uvd_v1_0.c

291

WREG32_P(SRBM_SOFT_RESET, 0, ~SOFT_RESET_UVD);

drivers/gpu/drm/radeon/uvd_v1_0.c

321

WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8));

drivers/gpu/drm/radeon/uvd_v1_0.c

323

WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3));

drivers/gpu/drm/radeon/uvd_v1_0.c

342

WREG32_P(UVD_SOFT_RESET, VCPU_SOFT_RESET, ~VCPU_SOFT_RESET);

drivers/gpu/drm/radeon/uvd_v1_0.c

344

WREG32_P(UVD_SOFT_RESET, 0, ~VCPU_SOFT_RESET);

drivers/gpu/drm/radeon/uvd_v1_0.c

355

WREG32_P(UVD_MASTINT_EN, 3<<1, ~(3 << 1));

drivers/gpu/drm/radeon/uvd_v1_0.c

379

WREG32_P(UVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f);

drivers/gpu/drm/radeon/uvd_v1_0.c

397

WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8));

drivers/gpu/drm/radeon/uvd_v1_0.c

398

WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3));

drivers/gpu/drm/radeon/uvd_v1_0.c

409

WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8));

drivers/gpu/drm/radeon/uvd_v1_0.c

410

WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3));

drivers/gpu/drm/radeon/vce_v1_0.c

222

WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16));

drivers/gpu/drm/radeon/vce_v1_0.c

223

WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);

drivers/gpu/drm/radeon/vce_v1_0.c

224

WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);

drivers/gpu/drm/radeon/vce_v1_0.c

227

WREG32_P(VCE_LMI_FW_PERIODIC_CTRL, 0x4, ~0x4);

drivers/gpu/drm/radeon/vce_v1_0.c

230

WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1);

drivers/gpu/drm/radeon/vce_v1_0.c

252

WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100);

drivers/gpu/drm/radeon/vce_v1_0.c

295

WREG32_P(VCE_STATUS, 1, ~1);

drivers/gpu/drm/radeon/vce_v1_0.c

311

WREG32_P(VCE_VCPU_CNTL, VCE_CLK_EN, ~VCE_CLK_EN);

drivers/gpu/drm/radeon/vce_v1_0.c

313

WREG32_P(VCE_SOFT_RESET,

drivers/gpu/drm/radeon/vce_v1_0.c

321

WREG32_P(VCE_SOFT_RESET, 0, ~(

drivers/gpu/drm/radeon/vce_v1_0.c

338

WREG32_P(VCE_SOFT_RESET, VCE_ECPU_SOFT_RESET, ~VCE_ECPU_SOFT_RESET);

drivers/gpu/drm/radeon/vce_v1_0.c

340

WREG32_P(VCE_SOFT_RESET, 0, ~VCE_ECPU_SOFT_RESET);

drivers/gpu/drm/radeon/vce_v1_0.c

346

WREG32_P(VCE_STATUS, 0, ~1);

drivers/gpu/drm/radeon/vce_v2_0.c

163

WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16));

drivers/gpu/drm/radeon/vce_v2_0.c

164

WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);

drivers/gpu/drm/radeon/vce_v2_0.c

165

WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);

drivers/gpu/drm/radeon/vce_v2_0.c

169

WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1);

drivers/gpu/drm/radeon/vce_v2_0.c

191

WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100);

drivers/gpu/drm/radeon/vce_v2_0.c

193

WREG32_P(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN,