WREG32_OR
WREG32_OR(mmDMA0_CORE_PROT + dma_offset, BIT(DMA0_CORE_PROT_VAL_SHIFT));
WREG32_OR(reg, asid);
WREG32_OR(mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset,
WREG32_OR(mmTPC0_EML_CFG_DBG_CNT + tpc_eml_offset,
WREG32_OR(reg, asid);
WREG32_OR(mmHDMI_INFOFRAME_CONTROL0 + offset,
WREG32_OR(mmAFMT_AUDIO_PACKET_CONTROL + offset,
WREG32_OR(mmVCE_VCPU_CNTL, 0x00100000);
WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
WREG32_OR(HDMI0_INFOFRAME_CONTROL1 + offset,
WREG32_OR(HDMI0_GC + offset, HDMI0_GC_AVMUTE);
WREG32_OR(DC_HPDx_INT_CONTROL(hpd), DC_HPDx_INT_POLARITY);
WREG32_OR(DC_HPDx_INT_CONTROL(i), DC_HPDx_INT_ACK);
WREG32_OR(DC_HPDx_INT_CONTROL(i), DC_HPDx_RX_INT_ACK);
WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + crtc_offsets[i],
WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset,
WREG32_OR(HDMI_GC + offset, HDMI_GC_AVMUTE);
WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
WREG32_OR(HDMI0_INFOFRAME_CONTROL1 + offset,
WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
WREG32_OR(HDMI0_VBI_PACKET_CONTROL + offset,
WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
WREG32_OR(HDMI0_GC + offset, HDMI0_GC_AVMUTE);
WREG32_OR(HDMI0_CONTROL + offset,
WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN);
WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN);
WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN);
WREG32_OR(DC_HPDx_INT_CONTROL(i), DC_HPDx_INT_ACK);
WREG32_OR(DC_HPDx_INT_CONTROL(i), DC_HPDx_RX_INT_ACK);