WREG32_NO_KIQ
WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000);
WREG32_NO_KIQ(mmMM_INDEX_HI, tmp);
WREG32_NO_KIQ(mmMM_DATA, *data++);
WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t) cursor.start) | 0x80000000);
WREG32_NO_KIQ(mmMM_INDEX_HI, tmp);
WREG32_NO_KIQ(mmMM_DATA, color);
WREG32_NO_KIQ(offset, value);
WREG32_NO_KIQ(mmRLC_SPM_VMID, data);
WREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2, inv_req);
WREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2, inv_req);
WREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2, inv_req);
WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2,
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0),
WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1),
WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2),
WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3),
WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp);
WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp);
WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0, req);
WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW1, data1);
WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW2, data2);
WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW3, data3);
WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp);
WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp);
WREG32_NO_KIQ(mmMAILBOX_CONTROL, reg);
WREG32_NO_KIQ(mmMAILBOX_CONTROL, reg);
WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0, reg);
WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp);
WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp);
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
WREG32_NO_KIQ(mmPCIE_INDEX, reg);
WREG32_NO_KIQ(mmPCIE_INDEX, reg);
WREG32_NO_KIQ(mmPCIE_DATA, v);
WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg));
WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg));
WREG32_NO_KIQ(mmSMC_IND_DATA_11, (v));