WREG32_FIELD
WREG32_FIELD(TPC0_CFG_MSS_CONFIG, tpc_offset,
WREG32_FIELD(TPC0_CFG_MSS_CONFIG, offset,
WREG32_FIELD(RLC_CP_SCHEDULERS, scheduler1, 0);
WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1);
WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1);
WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0);
WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1);
WREG32_FIELD(GRBM_CNTL, READ_TIMEOUT, 0xFF);
WREG32_FIELD(RLC_SRM_CNTL, AUTO_INCR_ADDR, 1);
WREG32_FIELD(RLC_SRM_CNTL, SRM_ENABLE, 1);
WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60);
WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3);
WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0);
WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PU_ENABLE, enable ? 1 : 0);
WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PD_ENABLE, enable ? 1 : 0);
WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 0 : 1);
WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 0);
WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 1);
WREG32_FIELD(CP_HQD_DEQUEUE_REQUEST, DEQUEUE_REQ, req);
WREG32_FIELD(CP_PQ_WPTR_POLL_CNTL, EN, 0);
WREG32_FIELD(CP_PQ_STATUS, DOORBELL_ENABLE, 1);
WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0);
WREG32_FIELD(RLC_PG_CNTL, DYN_PER_CU_PG_ENABLE, enable ? 1 : 0);
WREG32_FIELD(RLC_PG_CNTL, QUICK_PG_ENABLE, enable ? 1 : 0);
WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, enable ? 1 : 0);
WREG32_FIELD(RLC_PG_CNTL, GFX_PIPELINE_PG_ENABLE, enable ? 1 : 0);
WREG32_FIELD(RLC_MEM_SLP_CNTL, RLC_MEM_LS_EN, 1);
WREG32_FIELD(CP_MEM_SLP_CNTL, CP_MEM_LS_EN, 1);
WREG32_FIELD(CP_INT_CNTL_RING0, TIME_STAMP_INT_ENABLE,
WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_REG_INT_ENABLE,
WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_INSTR_INT_ENABLE,
WREG32_FIELD(CP_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, enable_flag);
WREG32_FIELD(CP_INT_CNTL_RING0, CP_ECC_ERROR_INT_ENABLE, enable_flag);
WREG32_FIELD(CP_INT_CNTL_RING1, CP_ECC_ERROR_INT_ENABLE, enable_flag);
WREG32_FIELD(CP_INT_CNTL_RING2, CP_ECC_ERROR_INT_ENABLE, enable_flag);
WREG32_FIELD(CPC_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, enable_flag);
WREG32_FIELD(CP_ME1_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
WREG32_FIELD(CP_ME1_PIPE1_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
WREG32_FIELD(CP_ME1_PIPE2_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
WREG32_FIELD(CP_ME1_PIPE3_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
WREG32_FIELD(CP_ME2_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
WREG32_FIELD(CP_ME2_PIPE1_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
WREG32_FIELD(CP_ME2_PIPE2_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
WREG32_FIELD(CP_ME2_PIPE3_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
WREG32_FIELD(SQ_INTERRUPT_MSG_CTRL, STALL,
WREG32_FIELD(UVD_CGC_GATE, REGS, 0);
WREG32_FIELD(UVD_CGC_GATE, REGS, 0);
WREG32_FIELD(UVD_MASTINT_EN, VCPU_EN, 0);
WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 1);
WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_UVD, 0);
WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 0);
WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 1);
WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 0);
WREG32_FIELD(UVD_RBC_RB_CNTL, RB_NO_FETCH, 0);
WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1);
WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 1);
WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1);
WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0);
WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_VCE, 1);
WREG32_FIELD(VCE_RB_ARB_CTRL, VCE_CGTT_OVERRIDE, override ? 1 : 0);
WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1);
WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0);
WREG32_FIELD(VCE_STATUS, JOB_BUSY, 1);
WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 1);
WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0);
WREG32_FIELD(VCE_STATUS, JOB_BUSY, 0);
WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 0);
WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1);
WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1);
WREG32_FIELD(VCE_SYS_INT_STATUS, VCE_SYS_INT_TRAP_INTERRUPT_INT, 1);
WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, 0);