drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c

2835

desc->wq_size = WQ_SIZE;

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c

2912

info->wq_size = WQ_SIZE;

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c

427

#define WQ_OFFSET (PARENT_SCRATCH_SIZE - WQ_SIZE)

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c

446

u32 wq[WQ_SIZE / sizeof(u32)];

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c

504

CIRC_SPACE(ce->parallel.guc.wqi_tail, ce->parallel.guc.wqi_head, WQ_SIZE)

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c

816

return (WQ_SIZE - ce->parallel.guc.wqi_tail);

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c

821

BUILD_BUG_ON(!is_power_of_2(WQ_SIZE));

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c

829

(WQ_SIZE - 1);

drivers/gpu/drm/xe/xe_guc_submit.c

1010

CIRC_SPACE(q->guc->wqi_tail, q->guc->wqi_head, WQ_SIZE)

drivers/gpu/drm/xe/xe_guc_submit.c

1088

xe_gt_assert(guc_to_gt(guc), q->guc->wqi_tail <= WQ_SIZE);

drivers/gpu/drm/xe/xe_guc_submit.c

2432

for (i = 0; i < WQ_SIZE / sizeof(u32); ++i)

drivers/gpu/drm/xe/xe_guc_submit.c

3122

i = (i + sizeof(u32)) % WQ_SIZE)

drivers/gpu/drm/xe/xe_guc_submit.c

3144

i = (i + sizeof(u32)) % WQ_SIZE)

drivers/gpu/drm/xe/xe_guc_submit.c

955

info.wq_size = WQ_SIZE;

drivers/gpu/drm/xe/xe_guc_submit.c

959

xe_map_memset(xe, &map, 0, 0, PARALLEL_SCRATCH_SIZE - WQ_SIZE);

drivers/gpu/drm/xe/xe_guc_submit.c

981

return (WQ_SIZE - q->guc->wqi_tail);

drivers/gpu/drm/xe/xe_guc_submit_types.h

129

u32 wq[WQ_SIZE / sizeof(u32)];

drivers/gpu/drm/xe/xe_guc_submit_types.h

27

#define WQ_OFFSET (PARALLEL_SCRATCH_SIZE - WQ_SIZE)

drivers/gpu/drm/xe/xe_guc_submit_types.h

61

u32 wq[WQ_SIZE / sizeof(u32)];

drivers/net/ethernet/huawei/hinic/hinic_hw_wq.c

450

num_q_pages = ALIGN(WQ_SIZE(wq), wq->wq_page_size) / wq->wq_page_size;