WORKER_VCPU_ID_1
set_expected_val((void *)data->test_pages, 0x0, WORKER_VCPU_ID_1);
set_expected_val((void *)data->test_pages, exp1, WORKER_VCPU_ID_1);
flush->processor_mask = BIT(WORKER_VCPU_ID_1);
flush->processor_mask = BIT(WORKER_VCPU_ID_1);
BIT_ULL(WORKER_VCPU_ID_1 / 64);
flush_ex->hv_vp_set.bank_contents[0] = BIT_ULL(WORKER_VCPU_ID_1 % 64);
flush_ex->hv_vp_set.valid_bank_mask = BIT_ULL(WORKER_VCPU_ID_1 / 64) |
flush_ex->hv_vp_set.bank_contents[0] = BIT_ULL(WORKER_VCPU_ID_1 % 64);
flush->processor_mask = BIT(WORKER_VCPU_ID_1);
flush->processor_mask = BIT(WORKER_VCPU_ID_1);
BIT_ULL(WORKER_VCPU_ID_1 / 64);
flush_ex->hv_vp_set.bank_contents[0] = BIT_ULL(WORKER_VCPU_ID_1 % 64);
flush_ex->hv_vp_set.valid_bank_mask = BIT_ULL(WORKER_VCPU_ID_1 / 64) |
flush_ex->hv_vp_set.bank_contents[0] = BIT_ULL(WORKER_VCPU_ID_1 % 64);
set_expected_val(addr_gva2hva(vm, data->test_pages), 0x0, WORKER_VCPU_ID_1);
vcpu[1] = vm_vcpu_add(vm, WORKER_VCPU_ID_1, worker_guest_code);
vcpu_set_msr(vcpu[1], HV_X64_MSR_VP_INDEX, WORKER_VCPU_ID_1);