drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

504

ranges->writer_wm_sets[0].wm_inst = WM_A;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

434

table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

347

.wm_inst = WM_A,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

384

.wm_inst = WM_A,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

470

table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

413

.wm_inst = WM_A,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

450

.wm_inst = WM_A,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

541

table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

307

.wm_inst = WM_A,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

344

.wm_inst = WM_A,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

430

table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

273

.wm_inst = WM_A,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

310

.wm_inst = WM_A,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

396

table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

766

.wm_inst = WM_A,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

803

.wm_inst = WM_A,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

912

table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

189

clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid = true;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

190

clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

191

clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

192

clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

193

clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

194

clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1392

ranges.reader_wm_sets[0].wm_inst = WM_A;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1397

ranges.writer_wm_sets[0].wm_inst = WM_A;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1404

ranges.reader_wm_sets[0].wm_inst = WM_A;

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

1409

ranges.writer_wm_sets[0].wm_inst = WM_A;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

2313

table_entry = &bw_params->wm_table.entries[WM_A];

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

770

.wm_inst = WM_A,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

807

.wm_inst = WM_A,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

844

.wm_inst = WM_A,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

881

.wm_inst = WM_A,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

918

.wm_inst = WM_A,

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

955

.wm_inst = WM_A,

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

294

if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) {

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

297

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

298

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

299

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

341

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

516

dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

669

base->bw_params->wm_table.nv_entries[WM_A].valid = true;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

670

base->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

671

base->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

672

base->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

673

base->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

674

base->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = 0;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

675

base->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

676

base->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

677

base->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

221

.wm_inst = WM_A,

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

258

.wm_inst = WM_A,

drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c

462

table_entry = &bw_params->wm_table.entries[WM_A];

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

458

if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

459

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

460

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

461

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

469

if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

474

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

476

dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

478

dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

211

clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

212

clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

213

clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us = fclk_change_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

214

clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

215

clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

216

clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

217

clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

218

clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

219

clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

220

clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2347

dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2385

dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2415

context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2576

context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2577

context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2578

context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2626

dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

2631

dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us;