drivers/phy/ti/phy-j721e-wiz.c

131

static const struct reg_field p_enable[WIZ_MAX_LANES] = {

drivers/phy/ti/phy-j721e-wiz.c

140

static const struct reg_field p_align[WIZ_MAX_LANES] = {

drivers/phy/ti/phy-j721e-wiz.c

147

static const struct reg_field p_raw_auto_start[WIZ_MAX_LANES] = {

drivers/phy/ti/phy-j721e-wiz.c

154

static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = {

drivers/phy/ti/phy-j721e-wiz.c

1542

if (num_lanes > WIZ_MAX_LANES) {

drivers/phy/ti/phy-j721e-wiz.c

161

static const struct reg_field p0_fullrt_div[WIZ_MAX_LANES] = {

drivers/phy/ti/phy-j721e-wiz.c

168

static const struct reg_field p0_mac_src_sel[WIZ_MAX_LANES] = {

drivers/phy/ti/phy-j721e-wiz.c

175

static const struct reg_field p0_rxfclk_sel[WIZ_MAX_LANES] = {

drivers/phy/ti/phy-j721e-wiz.c

182

static const struct reg_field p0_refclk_sel[WIZ_MAX_LANES] = {

drivers/phy/ti/phy-j721e-wiz.c

188

static const struct reg_field p_mac_div_sel0[WIZ_MAX_LANES] = {

drivers/phy/ti/phy-j721e-wiz.c

195

static const struct reg_field p_mac_div_sel1[WIZ_MAX_LANES] = {

drivers/phy/ti/phy-j721e-wiz.c

364

struct regmap_field *p_enable[WIZ_MAX_LANES];

drivers/phy/ti/phy-j721e-wiz.c

365

struct regmap_field *p_align[WIZ_MAX_LANES];

drivers/phy/ti/phy-j721e-wiz.c

366

struct regmap_field *p_raw_auto_start[WIZ_MAX_LANES];

drivers/phy/ti/phy-j721e-wiz.c

367

struct regmap_field *p_standard_mode[WIZ_MAX_LANES];

drivers/phy/ti/phy-j721e-wiz.c

368

struct regmap_field *p_mac_div_sel0[WIZ_MAX_LANES];

drivers/phy/ti/phy-j721e-wiz.c

369

struct regmap_field *p_mac_div_sel1[WIZ_MAX_LANES];

drivers/phy/ti/phy-j721e-wiz.c

370

struct regmap_field *p0_fullrt_div[WIZ_MAX_LANES];

drivers/phy/ti/phy-j721e-wiz.c

371

struct regmap_field *p0_mac_src_sel[WIZ_MAX_LANES];

drivers/phy/ti/phy-j721e-wiz.c

372

struct regmap_field *p0_rxfclk_sel[WIZ_MAX_LANES];

drivers/phy/ti/phy-j721e-wiz.c

373

struct regmap_field *p0_refclk_sel[WIZ_MAX_LANES];

drivers/phy/ti/phy-j721e-wiz.c

391

u32 lane_phy_type[WIZ_MAX_LANES];

drivers/phy/ti/phy-j721e-wiz.c

392

u32 master_lane_num[WIZ_MAX_LANES];