arch/arm/mach-omap2/cm3xxx.c

428

omap2_cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);

arch/arm/mach-omap2/cm3xxx.c

446

omap2_cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);

arch/arm/mach-omap2/cm3xxx.c

485

omap2_cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);

arch/arm/mach-omap2/cm3xxx.c

558

omap2_cm_write_mod_reg(cm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);

arch/arm/mach-omap2/cm3xxx.c

575

omap2_cm_write_mod_reg(cm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);

arch/arm/mach-omap2/cm3xxx.c

612

omap2_cm_write_mod_reg(cm_context.wkup_cm_autoidle, WKUP_MOD,

arch/arm/mach-omap2/cm3xxx.c

639

*ptr++ = omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);

arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c

349

.module_offs = WKUP_MOD,

arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c

481

.module_offs = WKUP_MOD,

arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c

496

.module_offs = WKUP_MOD,

arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c

511

.module_offs = WKUP_MOD,

arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c

526

.module_offs = WKUP_MOD,

arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

1002

.module_offs = WKUP_MOD,

arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

1017

.module_offs = WKUP_MOD,

arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

327

.module_offs = WKUP_MOD,

arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

674

.module_offs = WKUP_MOD,

arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

967

.module_offs = WKUP_MOD,

arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

982

.module_offs = WKUP_MOD,

arch/arm/mach-omap2/pm34xx.c

130

c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, OMAP3430_ST_IO_MASK |

arch/arm/mach-omap2/pm34xx.c

145

c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, ~(OMAP3430_ST_IO_MASK |

arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c

59

.prcm_offs = WKUP_MOD,

arch/arm/mach-omap2/prm2xxx.c

108

omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, WKUP_MOD,

arch/arm/mach-omap2/prm2xxx.c

111

omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTCTRL);

arch/arm/mach-omap2/prm2xxx.c

60

v = omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST);

arch/arm/mach-omap2/prm3xxx.c

306

WKUP_MOD, PM_WKEN);

arch/arm/mach-omap2/prm3xxx.c

311

WKUP_MOD, OMAP3430_PM_MPUGRPSEL);

arch/arm/mach-omap2/prm3xxx.c

353

omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);

arch/arm/mach-omap2/prm3xxx.c

387

omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,

arch/arm/mach-omap2/prm3xxx.c

389

omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,

arch/arm/mach-omap2/prm3xxx.c

391

omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);

arch/arm/mach-omap2/prm3xxx.c

407

omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,

arch/arm/mach-omap2/prm3xxx.c

410

omap_test_timeout(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST) &

arch/arm/mach-omap2/prm3xxx.c

416

omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,

arch/arm/mach-omap2/prm3xxx.c

419

omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, WKUP_MOD,

arch/arm/mach-omap2/prm3xxx.c

422

omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST);

arch/arm/mach-omap2/prm3xxx.c

437

omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,

arch/arm/mach-omap2/prm3xxx.c

453

v = omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST);