BNX2_WR
BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
BNX2_WR(bp, BNX2_EMAC_MODE, val);
BNX2_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
BNX2_WR(bp, BNX2_EMAC_TX_MODE, val);
BNX2_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
BNX2_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode);
BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode);
BNX2_WR(bp, BNX2_CTX_COMMAND, val);
BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
BNX2_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
BNX2_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
BNX2_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
BNX2_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
BNX2_WR(bp, BNX2_CTX_CTX_DATA, val);
BNX2_WR(bp, BNX2_CTX_CTX_CTRL,
BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
BNX2_WR(bp, BNX2_CTX_DATA_ADR, offset);
BNX2_WR(bp, BNX2_CTX_DATA, val);
BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
BNX2_WR(bp, BNX2_HC_COMMAND,
BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
BNX2_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));
BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));
BNX2_WR(bp, addr, val);
BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, code);
BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, code);
BNX2_WR(bp, addr, val);
BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
BNX2_WR(bp, BNX2_EMAC_MODE, val);
BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
BNX2_WR(bp, BNX2_EMAC_RX_MODE, BNX2_EMAC_RX_MODE_SORT_MODE);
BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
BNX2_WR(bp, BNX2_RPM_SORT_USER0, val);
BNX2_WR(bp, BNX2_RPM_SORT_USER0, val | BNX2_RPM_SORT_USER0_ENA);
BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
BNX2_WR(bp, BNX2_RPM_CONFIG, val);
BNX2_WR(bp, BNX2_EMAC_MODE, val);
BNX2_WR(bp, BNX2_RPM_CONFIG, val);
BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
BNX2_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
BNX2_WR(bp, BNX2_NVM_COMMAND,
BNX2_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE,
BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE,
BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);
BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);
BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
BNX2_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);
BNX2_WR(bp, BNX2_NVM_CFG1, flash->config1);
BNX2_WR(bp, BNX2_NVM_CFG2, flash->config2);
BNX2_WR(bp, BNX2_NVM_CFG3, flash->config3);
BNX2_WR(bp, BNX2_NVM_WRITE1, flash->write1);
BNX2_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
BNX2_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
BNX2_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
BNX2_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
BNX2_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
BNX2_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
BNX2_WR(bp, BNX2_MISC_ECO_HW_CTL,
BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
BNX2_WR(bp, BNX2_DMA_CONFIG, val);
BNX2_WR(bp, BNX2_TDMA_CONFIG, val);
BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
BNX2_WR(bp, BNX2_MQ_CONFIG, val);
BNX2_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
BNX2_WR(bp, BNX2_MQ_KNL_WIND_END, val);
BNX2_WR(bp, BNX2_RV2P_CONFIG, val);
BNX2_WR(bp, BNX2_TBDR_CONFIG, val);
BNX2_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
BNX2_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
BNX2_WR(bp, BNX2_HC_STATUS_ADDR_L,
BNX2_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
BNX2_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
BNX2_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
BNX2_WR(bp, BNX2_HC_COMP_PROD_TRIP,
BNX2_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
BNX2_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
BNX2_WR(bp, BNX2_HC_COM_TICKS,
BNX2_WR(bp, BNX2_HC_CMD_TICKS,
BNX2_WR(bp, BNX2_HC_STATS_TICKS, 0);
BNX2_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
BNX2_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
BNX2_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
BNX2_WR(bp, BNX2_HC_CONFIG, val);
BNX2_WR(bp, base,
BNX2_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
BNX2_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
BNX2_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
BNX2_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
BNX2_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
BNX2_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
BNX2_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
BNX2_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
BNX2_WR(bp, BNX2_TSCH_TSS_CFG, 0);
BNX2_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
BNX2_WR(bp, BNX2_RLUP_RSS_DATA, tbl_32);
BNX2_WR(bp, BNX2_RLUP_RSS_COMMAND, (i >> 3) |
BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
BNX2_WR(bp, BNX2_HC_COMMAND,
BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
BNX2_WR(bp, BNX2_HC_COMMAND,
BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
BNX2_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
BNX2_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
BNX2_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
BNX2_WR(bp, BNX2_TBDC_BD_ADDR, i);
BNX2_WR(bp, BNX2_TBDC_CAM_OPCODE,
BNX2_WR(bp, BNX2_TBDC_COMMAND, BNX2_TBDC_COMMAND_CMD_REG_ARB);
BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
BNX2_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
BNX2_WR(bp, BNX2_EMAC_LED, 0);
BNX2_WR(bp, BNX2_MISC_CFG, bp->leds_save);
BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG,
BNX2_WR(bp, PCI_COMMAND, reg);