VTD_PAGE_SHIFT
start &= GENMASK(BITS_PER_LONG - 1, VTD_PAGE_SHIFT);
*size_order = sz_lg2 - VTD_PAGE_SHIFT;
return BIT_ULL(VTD_PAGE_SHIFT + VTD_STRIDE_SHIFT * (level - 1));
iova >> VTD_PAGE_SHIFT, path[5], path[4], path[3]);
pci_prepare_ats(pdev, VTD_PAGE_SHIFT);
pgtable_walk(iommu, addr >> VTD_PAGE_SHIFT, bus, devfn, pgtable, level);
if (!pci_enable_ats(pdev, VTD_PAGE_SHIFT))
return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT;
return npages << VTD_PAGE_SHIFT;
addr |= (1ULL << (VTD_PAGE_SHIFT + mask - 1)) - 1;
unsigned long mask = 1UL << (VTD_PAGE_SHIFT + size_order - 1);
desc->qw1 |= GENMASK_ULL(size_order + VTD_PAGE_SHIFT - 1,
VTD_PAGE_SHIFT);
#define VTD_PAGE_SIZE (1UL << VTD_PAGE_SHIFT)
#define VTD_PAGE_MASK (((u64)-1) << VTD_PAGE_SHIFT)
#define MAX_AGAW_PFN_WIDTH (MAX_AGAW_WIDTH - VTD_PAGE_SHIFT)
qi_flush_dev_iotlb(iommu, sid, pfsid, qdep, 0, 64 - VTD_PAGE_SHIFT);
qi_flush_dev_iotlb_pasid(iommu, sid, pfsid, pasid, qdep, 0, 64 - VTD_PAGE_SHIFT);
event.fault.prm.addr = (u64)desc->addr << VTD_PAGE_SHIFT;
address = (u64)req->addr << VTD_PAGE_SHIFT;