BNX2_RD
val = BNX2_RD(bp, BNX2_EMAC_MODE);
val = BNX2_RD(bp, BNX2_EMAC_TX_MODE);
val = BNX2_RD(bp, BNX2_EMAC_STATUS);
mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE);
mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE);
val = BNX2_RD(bp, BNX2_CTX_COMMAND);
val = BNX2_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
val = BNX2_RD(bp, BNX2_PCICFG_REG_WINDOW);
val = BNX2_RD(bp, BNX2_CTX_CTX_CTRL);
(BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS) &
BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
msi_ctrl = BNX2_RD(bp, BNX2_PCICFG_MSI_CONTROL);
BNX2_RD(bp, BNX2_HC_COMMAND);
val = BNX2_RD(bp, BNX2_EMAC_MODE);
val = BNX2_RD(bp, BNX2_RPM_CONFIG);
val = BNX2_RD(bp, BNX2_EMAC_MODE);
val = BNX2_RD(bp, BNX2_RPM_CONFIG);
val = BNX2_RD(bp, BNX2_NVM_SW_ARB);
val = BNX2_RD(bp, BNX2_NVM_SW_ARB);
val = BNX2_RD(bp, BNX2_MISC_CFG);
val = BNX2_RD(bp, BNX2_NVM_COMMAND);
val = BNX2_RD(bp, BNX2_MISC_CFG);
val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE);
val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE);
val = BNX2_RD(bp, BNX2_NVM_COMMAND);
val = BNX2_RD(bp, BNX2_NVM_COMMAND);
__be32 v = cpu_to_be32(BNX2_RD(bp, BNX2_NVM_READ));
if (BNX2_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
val = BNX2_RD(bp, BNX2_NVM_CFG1);
val = BNX2_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);
val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);
val = BNX2_RD(bp, BNX2_PCICFG_DEVICE_CONTROL);
val = BNX2_RD(bp, BNX2_MISC_ID);
BNX2_RD(bp, BNX2_MISC_COMMAND);
val = BNX2_RD(bp, BNX2_PCICFG_MISC_CONFIG);
val = BNX2_RD(bp, BNX2_PCI_SWAP_DIAG0);
val = BNX2_RD(bp, BNX2_TDMA_CONFIG);
val = BNX2_RD(bp, BNX2_MQ_CONFIG);
val = BNX2_RD(bp, BNX2_TBDR_CONFIG);
val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);
BNX2_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
bp->hc_cmd = BNX2_RD(bp, BNX2_HC_COMMAND);
BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
val = BNX2_RD(bp, BNX2_MQ_MAP_L2_5);
val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);
val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);
val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);
BNX2_RD(bp, BNX2_HC_COMMAND);
BNX2_RD(bp, BNX2_HC_COMMAND);
val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
status_idx = BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
BNX2_RD(bp, BNX2_HC_COMMAND);
if ((BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
BNX2_RD(bp, BNX2_PCI_MSIX_CONTROL);
BNX2_RD(bp, BNX2_TBDC_STATUS) & BNX2_TBDC_STATUS_FREE_CNT);
while ((BNX2_RD(bp, BNX2_TBDC_COMMAND) &
cid = BNX2_RD(bp, BNX2_TBDC_CID);
bdidx = BNX2_RD(bp, BNX2_TBDC_BIDX);
valid = BNX2_RD(bp, BNX2_TBDC_CAM_OPCODE);
BNX2_RD(bp, BNX2_EMAC_TX_STATUS),
BNX2_RD(bp, BNX2_EMAC_RX_STATUS));
BNX2_RD(bp, BNX2_RPM_MGMT_PKT_CTRL));
BNX2_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS));
BNX2_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE));
*p++ = BNX2_RD(bp, offset);
bp->leds_save = BNX2_RD(bp, BNX2_MISC_CFG);
u32 val = BNX2_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
reg = BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS);
clkreg = BNX2_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
bp->chip_id = BNX2_RD(bp, BNX2_MISC_ID);
reg = BNX2_RD(bp, PCI_COMMAND);
!(BNX2_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {