VPU_HW_BTRS_LNL_VPU_STATUS
return REGB_POLL_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, READY, exp_val, PLL_TIMEOUT_US);
return REGB_POLL_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, CLOCK_RESOURCE_OWN_ACK, 1, TIMEOUT_US);
u32 val = REGB_RD32(VPU_HW_BTRS_LNL_VPU_STATUS);
val = REG_CLR_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, PERF_CLK, val);
val = REG_SET_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, PERF_CLK, val);
REGB_WR32(VPU_HW_BTRS_LNL_VPU_STATUS, val);
u32 val = REGB_RD32(VPU_HW_BTRS_LNL_VPU_STATUS);
val = REG_SET_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, DISABLE_CLK_RELINQUISH, val);
REGB_WR32(VPU_HW_BTRS_LNL_VPU_STATUS, val);
val = REGB_RD32(VPU_HW_BTRS_LNL_VPU_STATUS);
return REG_TEST_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, READY, val) &&
REG_TEST_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, IDLE, val);
return REGB_POLL_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, IDLE, 0x1, IDLE_TIMEOUT_US);
u32 reg = REGB_RD32(VPU_HW_BTRS_LNL_VPU_STATUS);
return REG_GET_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, PLATFORM, reg);