WB_ENABLE
REG_UPDATE(WB_ENABLE, WB_ENABLE, 1);
REG_UPDATE(WB_ENABLE, WB_ENABLE, 0);
type WB_ENABLE;\
uint32_t WB_ENABLE;
SRI(WB_ENABLE, CNV, inst),\
SF(CNV0_WB_ENABLE, WB_ENABLE, mask_sh),\
REG_UPDATE(WB_ENABLE, WB_ENABLE, 1);
REG_UPDATE(WB_ENABLE, WB_ENABLE, 0);
REG_GET(WB_ENABLE, WB_ENABLE, &wb_enabled);
type WB_ENABLE;\
SRI2_DWB(WB_ENABLE, CNV, inst),\
uint32_t WB_ENABLE;
SF_DWB(WB_ENABLE, WB_ENABLE, mask_sh),\
WB_ENABLE | GAM_ENABLES | DPC_BLCENABLE |
CSC_ENABLE | GAM_ENABLES | WB_ENABLE |
CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
isc->try_config.bits_pipeline = WB_ENABLE | DPC_BLCENABLE;
(WB_ENABLE | CFA_ENABLE | CC_ENABLE | GAM_ENABLES | CSC_ENABLE | \
(WB_ENABLE | CFA_ENABLE | CC_ENABLE | GAM_ENABLES | CSC_ENABLE | \
WB_ENABLE | GAM_ENABLES | DPC_BLCENABLE |
CSC_ENABLE | GAM_ENABLES | WB_ENABLE |
CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
isc->try_config.bits_pipeline = WB_ENABLE | DPC_BLCENABLE;
(WB_ENABLE | CFA_ENABLE | CC_ENABLE | GAM_ENABLES | CSC_ENABLE | \
(WB_ENABLE | CFA_ENABLE | CC_ENABLE | GAM_ENABLES | CSC_ENABLE | \