drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

1566

offsetof(SMU7_Fusion_DpmTable, VceBootLevel),

drivers/gpu/drm/amd/pm/powerplay/inc/smu72_discrete.h

280

uint8_t VceBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu73_discrete.h

254

uint8_t VceBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu74_discrete.h

299

uint8_t VceBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu75_discrete.h

304

uint8_t VceBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_discrete.h

338

uint8_t VceBootLevel;

drivers/gpu/drm/amd/pm/powerplay/inc/smu7_fusion.h

232

uint8_t VceBootLevel;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1569

table->VceBootLevel = 0;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2013

table->VceBootLevel = 0;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

2909

VceBootLevel, 0); /* temp hard code to level 0, vce can set min evclk*/

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1430

table->VceBootLevel = 0;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2328

case VceBootLevel:

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2329

return offsetof(SMU73_Discrete_DpmTable, VceBootLevel);

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2407

smu_data->smc_state_table.VceBootLevel =

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2410

smu_data->smc_state_table.VceBootLevel = 0;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2413

offsetof(SMU73_Discrete_DpmTable, VceBootLevel);

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2419

mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

2426

(uint32_t)1 << smu_data->smc_state_table.VceBootLevel,

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1379

table->VceBootLevel = 0;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2323

smu_data->smc_state_table.VceBootLevel =

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2326

smu_data->smc_state_table.VceBootLevel = 0;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2329

offsetof(SMU74_Discrete_DpmTable, VceBootLevel);

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2335

mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2342

(uint32_t)1 << smu_data->smc_state_table.VceBootLevel,

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2453

case VceBootLevel:

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2454

return offsetof(SMU74_Discrete_DpmTable, VceBootLevel);

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1381

table->VceBootLevel = 0;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2639

case VceBootLevel:

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2640

return offsetof(SMU72_Discrete_DpmTable, VceBootLevel);

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2719

smu_data->smc_state_table.VceBootLevel =

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2723

offsetof(SMU72_Discrete_DpmTable, VceBootLevel);

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2729

mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

2737

(uint32_t)1 << smu_data->smc_state_table.VceBootLevel,

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1208

table->VceBootLevel = 0;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

2188

case VceBootLevel:

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

2189

return offsetof(SMU75_Discrete_DpmTable, VceBootLevel);

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

372

smu_data->smc_state_table.VceBootLevel =

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

375

smu_data->smc_state_table.VceBootLevel = 0;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

378

offsetof(SMU75_Discrete_DpmTable, VceBootLevel);

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

384

mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

391

(uint32_t)1 << smu_data->smc_state_table.VceBootLevel,

drivers/gpu/drm/radeon/ci_dpm.c

3573

table->VceBootLevel = 0;

drivers/gpu/drm/radeon/ci_dpm.c

4077

pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev);

drivers/gpu/drm/radeon/ci_dpm.c

4080

tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel);

drivers/gpu/drm/radeon/kv_dpm.c

1313

offsetof(SMU7_Fusion_DpmTable, VceBootLevel),

drivers/gpu/drm/radeon/smu7_discrete.h

324

uint8_t VceBootLevel;

drivers/gpu/drm/radeon/smu7_fusion.h

232

uint8_t VceBootLevel;