VLP_CLK_CFG_UPDATE
0, 3, 7, VLP_CLK_CFG_UPDATE, TOP_MUX_SCP_SHIFT,
VLP_CLK_CFG_UPDATE, TOP_MUX_SCP_SPI_SHIFT),
VLP_CLK_CFG_UPDATE, TOP_MUX_SCP_IIC_SHIFT),
VLP_CLK_CFG_UPDATE, TOP_MUX_SCP_IIC_HS_SHIFT),
VLP_CLK_CFG_UPDATE, TOP_MUX_PWRAP_ULPOSC_SHIFT),
VLP_CLK_CFG_UPDATE, TOP_MUX_SPMI_M_TIA_32K_SHIFT),
VLP_CLK_CFG_UPDATE, TOP_MUX_APXGPT_26M_B_SHIFT),
VLP_CLK_CFG_UPDATE, TOP_MUX_DPSW_SHIFT),
VLP_CLK_CFG_UPDATE, TOP_MUX_DPSW_CENTRAL_SHIFT),
VLP_CLK_CFG_UPDATE, TOP_MUX_SPMI_M_MST_SHIFT),
VLP_CLK_CFG_UPDATE, TOP_MUX_DVFSRC_SHIFT),
24, 3, 31, VLP_CLK_CFG_UPDATE, TOP_MUX_PWM_VLP_SHIFT,
VLP_CLK_CFG_UPDATE, TOP_MUX_AXI_VLP_SHIFT),
VLP_CLK_CFG_UPDATE, TOP_MUX_SYSTIMER_26M_SHIFT),
VLP_CLK_CFG_UPDATE, TOP_MUX_SSPM_SHIFT),
VLP_CLK_CFG_UPDATE, TOP_MUX_SRCK_SHIFT),
0, 4, 7, VLP_CLK_CFG_UPDATE, TOP_MUX_CAMTG0_SHIFT,
8, 4, 15, VLP_CLK_CFG_UPDATE, TOP_MUX_CAMTG1_SHIFT,
16, 4, 23, VLP_CLK_CFG_UPDATE, TOP_MUX_CAMTG2_SHIFT,
24, 4, 31, VLP_CLK_CFG_UPDATE, TOP_MUX_CAMTG3_SHIFT,
0, 4, 7, VLP_CLK_CFG_UPDATE, TOP_MUX_CAMTG4_SHIFT,
8, 4, 15, VLP_CLK_CFG_UPDATE, TOP_MUX_CAMTG5_SHIFT,
16, 4, 23, VLP_CLK_CFG_UPDATE, TOP_MUX_CAMTG6_SHIFT,
24, 4, 31, VLP_CLK_CFG_UPDATE, TOP_MUX_CAMTG7_SHIFT,
VLP_CLK_CFG_UPDATE, TOP_MUX_SSPM_26M_SHIFT),
VLP_CLK_CFG_UPDATE, TOP_MUX_ULPOSC_SSPM_SHIFT),
VLP_CLK_CFG_UPDATE, TOP_MUX_VLP_PBUS_26M_SHIFT),
VLP_CLK_CFG_UPDATE, TOP_MUX_DEBUG_ERR_FLAG_VLP_26M_SHIFT),
VLP_CLK_CFG_UPDATE, TOP_MUX_DPMSRDMA_SHIFT),
VLP_CLK_CFG_UPDATE, TOP_MUX_VLP_PBUS_156M_SHIFT),