Symbol: VX_MASK
arch/powerpc/xmon/ppc-opc.c
2527
#define VXVA_MASK (VX_MASK | (0x1f << 16))
arch/powerpc/xmon/ppc-opc.c
2530
#define VXVB_MASK (VX_MASK | (0x1f << 11))
arch/powerpc/xmon/ppc-opc.c
2533
#define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11))
arch/powerpc/xmon/ppc-opc.c
2536
#define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16))
arch/powerpc/xmon/ppc-opc.c
2539
#define VXUIMM4_MASK (VX_MASK | (0x1 << 20))
arch/powerpc/xmon/ppc-opc.c
2542
#define VXUIMM3_MASK (VX_MASK | (0x3 << 19))
arch/powerpc/xmon/ppc-opc.c
2545
#define VXUIMM2_MASK (VX_MASK | (0x7 << 18))
arch/powerpc/xmon/ppc-opc.c
2548
#define VXPS_MASK (VX_MASK & ~(0x1 << 9))
arch/powerpc/xmon/ppc-opc.c
2551
#define VXVAPS_MASK ((VX_MASK | (0x1f << 16)) & ~(0x1 << 9))
arch/powerpc/xmon/ppc-opc.c
3088
{"vaddubm", VX (4, 0), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3090
{"vmaxub", VX (4, 2), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3091
{"vrlb", VX (4, 4), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3094
{"vmuloub", VX (4, 8), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3095
{"vaddfp", VX (4, 10), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3097
{"vmrghb", VX (4, 12), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3099
{"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3163
{"vadduhm", VX (4, 64), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3164
{"vmul10ecuq", VX (4, 65), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3165
{"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3166
{"vrlh", VX (4, 68), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3169
{"vmulouh", VX (4, 72), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3170
{"vsubfp", VX (4, 74), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3172
{"vmrghh", VX (4, 76), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3174
{"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3184
{"vadduwm", VX (4, 128), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3185
{"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3186
{"vrlw", VX (4, 132), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3187
{"vrlwmi", VX (4, 133), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3190
{"vmulouw", VX (4, 136), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3191
{"vmuluwm", VX (4, 137), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3192
{"vmrghw", VX (4, 140), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3193
{"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3199
{"vaddudm", VX (4, 192), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3200
{"vmaxud", VX (4, 194), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3201
{"vrld", VX (4, 196), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3202
{"vrldmi", VX (4, 197), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3205
{"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3210
{"vadduqm", VX (4, 256), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3211
{"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3212
{"vslb", VX (4, 260), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3214
{"vmulosb", VX (4, 264), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3216
{"vmrglb", VX (4, 268), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3217
{"vpkshus", VX (4, 270), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3224
{"vaddcuq", VX (4, 320), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3225
{"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3226
{"vslh", VX (4, 324), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3228
{"vmulosh", VX (4, 328), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3230
{"vmrglh", VX (4, 332), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3231
{"vpkswus", VX (4, 334), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3238
{"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3239
{"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3240
{"vslw", VX (4, 388), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3241
{"vrlwnm", VX (4, 389), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3243
{"vmulosw", VX (4, 392), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3245
{"vmrglw", VX (4, 396), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3246
{"vpkshss", VX (4, 398), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3249
{"vmaxsd", VX (4, 450), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3250
{"vsl", VX (4, 452), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3251
{"vrldnm", VX (4, 453), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3254
{"vpkswss", VX (4, 462), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3259
{"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3260
{"vaddubs", VX (4, 512), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3262
{"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
arch/powerpc/xmon/ppc-opc.c
3263
{"vminub", VX (4, 514), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3264
{"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3265
{"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}},
arch/powerpc/xmon/ppc-opc.c
3266
{"vsrb", VX (4, 516), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3267
{"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}},
arch/powerpc/xmon/ppc-opc.c
3268
{"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
arch/powerpc/xmon/ppc-opc.c
3270
{"evabs", VX (4, 520), VX_MASK, PPCSPE, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3271
{"vmuleub", VX (4, 520), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3272
{"evneg", VX (4, 521), VX_MASK, PPCSPE, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3273
{"evextsb", VX (4, 522), VX_MASK, PPCSPE, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3275
{"evextsh", VX (4, 523), VX_MASK, PPCSPE, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3276
{"evrndw", VX (4, 524), VX_MASK, PPCSPE, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3279
{"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3280
{"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3282
{"brinc", VX (4, 527), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3285
{"evand", VX (4, 529), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3286
{"evandc", VX (4, 530), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3287
{"evxor", VX (4, 534), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3288
{"evmr", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
arch/powerpc/xmon/ppc-opc.c
3289
{"evor", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3290
{"evnor", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3291
{"evnot", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
arch/powerpc/xmon/ppc-opc.c
3293
{"eveqv", VX (4, 537), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3294
{"evorc", VX (4, 539), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3295
{"evnand", VX (4, 542), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3296
{"evsrwu", VX (4, 544), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3297
{"evsrws", VX (4, 545), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3298
{"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
arch/powerpc/xmon/ppc-opc.c
3299
{"evsrwis", VX (4, 547), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
arch/powerpc/xmon/ppc-opc.c
3300
{"evslw", VX (4, 548), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3301
{"evslwi", VX (4, 550), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
arch/powerpc/xmon/ppc-opc.c
3302
{"evrlw", VX (4, 552), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3303
{"evsplati", VX (4, 553), VX_MASK, PPCSPE, 0, {RS, SIMM}},
arch/powerpc/xmon/ppc-opc.c
3304
{"evrlwi", VX (4, 554), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
arch/powerpc/xmon/ppc-opc.c
3305
{"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, 0, {RS, SIMM}},
arch/powerpc/xmon/ppc-opc.c
3306
{"evmergehi", VX (4, 556), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3307
{"evmergelo", VX (4, 557), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3308
{"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3309
{"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3310
{"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3311
{"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3312
{"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3313
{"evcmplts", VX (4, 563), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3314
{"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3316
{"vadduhs", VX (4, 576), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3317
{"vmul10euq", VX (4, 577), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3318
{"vminuh", VX (4, 578), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3319
{"vsrh", VX (4, 580), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3321
{"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3329
{"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3330
{"vadduws", VX (4, 640), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3331
{"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3332
{"vminuw", VX (4, 642), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3333
{"evfsabs", VX (4, 644), VX_MASK, PPCSPE, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3334
{"vsrw", VX (4, 644), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3335
{"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3336
{"evfsneg", VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3338
{"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3339
{"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3340
{"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3342
{"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3345
{"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3346
{"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3348
{"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}},
arch/powerpc/xmon/ppc-opc.c
3349
{"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}},
arch/powerpc/xmon/ppc-opc.c
3350
{"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}},
arch/powerpc/xmon/ppc-opc.c
3351
{"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}},
arch/powerpc/xmon/ppc-opc.c
3352
{"evfsctui", VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}},
arch/powerpc/xmon/ppc-opc.c
3353
{"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}},
arch/powerpc/xmon/ppc-opc.c
3354
{"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}},
arch/powerpc/xmon/ppc-opc.c
3355
{"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}},
arch/powerpc/xmon/ppc-opc.c
3356
{"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, 0, {RS, RB}},
arch/powerpc/xmon/ppc-opc.c
3358
{"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, 0, {RS, RB}},
arch/powerpc/xmon/ppc-opc.c
3359
{"evfststgt", VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3360
{"evfststlt", VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3361
{"evfststeq", VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3363
{"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3364
{"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3365
{"vminud", VX (4, 706), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3366
{"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3367
{"vsr", VX (4, 708), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3368
{"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3369
{"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3372
{"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3373
{"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3375
{"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3377
{"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3378
{"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3380
{"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}},
arch/powerpc/xmon/ppc-opc.c
3381
{"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}},
arch/powerpc/xmon/ppc-opc.c
3382
{"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}},
arch/powerpc/xmon/ppc-opc.c
3383
{"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}},
arch/powerpc/xmon/ppc-opc.c
3384
{"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}},
arch/powerpc/xmon/ppc-opc.c
3385
{"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}},
arch/powerpc/xmon/ppc-opc.c
3386
{"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}},
arch/powerpc/xmon/ppc-opc.c
3387
{"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}},
arch/powerpc/xmon/ppc-opc.c
3388
{"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}},
arch/powerpc/xmon/ppc-opc.c
3389
{"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}},
arch/powerpc/xmon/ppc-opc.c
3391
{"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}},
arch/powerpc/xmon/ppc-opc.c
3392
{"efststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3393
{"efststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3394
{"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3395
{"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3396
{"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3397
{"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, 0, {RS, RB}},
arch/powerpc/xmon/ppc-opc.c
3398
{"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, 0, {RS, RB}},
arch/powerpc/xmon/ppc-opc.c
3399
{"efdabs", VX (4, 740), VX_MASK, PPCEFS, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3400
{"efdnabs", VX (4, 741), VX_MASK, PPCEFS, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3401
{"efdneg", VX (4, 742), VX_MASK, PPCEFS, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3402
{"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3403
{"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3404
{"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, 0, {RS, RB}},
arch/powerpc/xmon/ppc-opc.c
3405
{"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, 0, {RS, RB}},
arch/powerpc/xmon/ppc-opc.c
3406
{"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3407
{"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3408
{"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3409
{"efdcfs", VX (4, 751), VX_MASK, PPCEFS, 0, {RS, RB}},
arch/powerpc/xmon/ppc-opc.c
3410
{"efdcfui", VX (4, 752), VX_MASK, PPCEFS, 0, {RS, RB}},
arch/powerpc/xmon/ppc-opc.c
3411
{"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, 0, {RS, RB}},
arch/powerpc/xmon/ppc-opc.c
3412
{"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, 0, {RS, RB}},
arch/powerpc/xmon/ppc-opc.c
3413
{"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, 0, {RS, RB}},
arch/powerpc/xmon/ppc-opc.c
3414
{"efdctui", VX (4, 756), VX_MASK, PPCEFS, 0, {RS, RB}},
arch/powerpc/xmon/ppc-opc.c
3415
{"efdctsi", VX (4, 757), VX_MASK, PPCEFS, 0, {RS, RB}},
arch/powerpc/xmon/ppc-opc.c
3416
{"efdctuf", VX (4, 758), VX_MASK, PPCEFS, 0, {RS, RB}},
arch/powerpc/xmon/ppc-opc.c
3417
{"efdctsf", VX (4, 759), VX_MASK, PPCEFS, 0, {RS, RB}},
arch/powerpc/xmon/ppc-opc.c
3418
{"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, 0, {RS, RB}},
arch/powerpc/xmon/ppc-opc.c
3420
{"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, 0, {RS, RB}},
arch/powerpc/xmon/ppc-opc.c
3421
{"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3422
{"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3423
{"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3424
{"evlddx", VX (4, 768), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3425
{"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3426
{"evldd", VX (4, 769), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
arch/powerpc/xmon/ppc-opc.c
3427
{"evldwx", VX (4, 770), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3428
{"vminsb", VX (4, 770), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3429
{"evldw", VX (4, 771), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
arch/powerpc/xmon/ppc-opc.c
3430
{"evldhx", VX (4, 772), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3431
{"vsrab", VX (4, 772), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3432
{"evldh", VX (4, 773), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
arch/powerpc/xmon/ppc-opc.c
3434
{"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3435
{"vmulesb", VX (4, 776), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3436
{"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
arch/powerpc/xmon/ppc-opc.c
3437
{"vcfux", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
arch/powerpc/xmon/ppc-opc.c
3438
{"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
arch/powerpc/xmon/ppc-opc.c
3439
{"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3442
{"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
arch/powerpc/xmon/ppc-opc.c
3443
{"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3444
{"vpkpx", VX (4, 782), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3445
{"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
arch/powerpc/xmon/ppc-opc.c
3447
{"evlwhex", VX (4, 784), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3449
{"evlwhe", VX (4, 785), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
arch/powerpc/xmon/ppc-opc.c
3450
{"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3451
{"evlwhou", VX (4, 789), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
arch/powerpc/xmon/ppc-opc.c
3452
{"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3453
{"evlwhos", VX (4, 791), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
arch/powerpc/xmon/ppc-opc.c
3455
{"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3457
{"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
arch/powerpc/xmon/ppc-opc.c
3458
{"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3459
{"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
arch/powerpc/xmon/ppc-opc.c
3460
{"evstddx", VX (4, 800), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3461
{"evstdd", VX (4, 801), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
arch/powerpc/xmon/ppc-opc.c
3462
{"evstdwx", VX (4, 802), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3463
{"evstdw", VX (4, 803), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
arch/powerpc/xmon/ppc-opc.c
3464
{"evstdhx", VX (4, 804), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3465
{"evstdh", VX (4, 805), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
arch/powerpc/xmon/ppc-opc.c
3466
{"evstwhex", VX (4, 816), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3467
{"evstwhe", VX (4, 817), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
arch/powerpc/xmon/ppc-opc.c
3468
{"evstwhox", VX (4, 820), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3469
{"evstwho", VX (4, 821), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
arch/powerpc/xmon/ppc-opc.c
3470
{"evstwwex", VX (4, 824), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3471
{"evstwwe", VX (4, 825), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
arch/powerpc/xmon/ppc-opc.c
3472
{"evstwwox", VX (4, 828), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3473
{"evstwwo", VX (4, 829), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
arch/powerpc/xmon/ppc-opc.c
3474
{"vaddshs", VX (4, 832), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3475
{"bcdcpsgn.", VX (4, 833), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3476
{"vminsh", VX (4, 834), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3477
{"vsrah", VX (4, 836), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3479
{"vmulesh", VX (4, 840), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3480
{"vcfsx", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
arch/powerpc/xmon/ppc-opc.c
3481
{"vcsxwfp", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
arch/powerpc/xmon/ppc-opc.c
3491
{"vaddsws", VX (4, 896), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3492
{"vminsw", VX (4, 898), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3493
{"vsraw", VX (4, 900), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3495
{"vmulesw", VX (4, 904), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3496
{"vctuxs", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
arch/powerpc/xmon/ppc-opc.c
3497
{"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
arch/powerpc/xmon/ppc-opc.c
3502
{"vminsd", VX (4, 962), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3503
{"vsrad", VX (4, 964), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3506
{"vctsxs", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
arch/powerpc/xmon/ppc-opc.c
3507
{"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
arch/powerpc/xmon/ppc-opc.c
3514
{"vsububm", VX (4,1024), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3516
{"vavgub", VX (4,1026), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3517
{"vabsdub", VX (4,1027), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3518
{"evmhessf", VX (4,1027), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3519
{"vand", VX (4,1028), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3524
{"evmhossf", VX (4,1031), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3525
{"vpmsumb", VX (4,1032), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3526
{"evmheumi", VX (4,1032), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3527
{"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3528
{"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3529
{"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3530
{"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3531
{"vslo", VX (4,1036), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3532
{"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3533
{"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3538
{"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3539
{"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3540
{"evmheumia", VX (4,1064), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3541
{"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3542
{"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3543
{"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3544
{"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3545
{"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3546
{"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3548
{"vavguh", VX (4,1090), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3549
{"vabsduh", VX (4,1091), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3550
{"vandc", VX (4,1092), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3555
{"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3556
{"vpmsumh", VX (4,1096), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3557
{"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3558
{"vminfp", VX (4,1098), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3559
{"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3560
{"vsro", VX (4,1100), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3561
{"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3562
{"vpkudum", VX (4,1102), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3563
{"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3564
{"evmwssf", VX (4,1107), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3566
{"evmwumi", VX (4,1112), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3568
{"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3569
{"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3574
{"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3575
{"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3576
{"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3577
{"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3578
{"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3579
{"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3580
{"evmwumia", VX (4,1144), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3581
{"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3582
{"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3583
{"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3584
{"bcdus.", VX (4,1153), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3585
{"vavguw", VX (4,1154), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3586
{"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3587
{"vmr", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VBA}},
arch/powerpc/xmon/ppc-opc.c
3588
{"vor", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3590
{"vpmsumw", VX (4,1160), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3598
{"vsubudm", VX (4,1216), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3599
{"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3601
{"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3602
{"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3603
{"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3604
{"evmra", VX (4,1220), VX_MASK, PPCSPE, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3605
{"vxor", VX (4,1220), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3606
{"evdivws", VX (4,1222), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3611
{"evdivwu", VX (4,1223), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3612
{"vpmsumd", VX (4,1224), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3613
{"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3614
{"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3615
{"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3616
{"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, 0, {RS, RA}},
arch/powerpc/xmon/ppc-opc.c
3617
{"vpkudus", VX (4,1230), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3624
{"vsubuqm", VX (4,1280), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3625
{"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3627
{"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3628
{"vavgsb", VX (4,1282), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3629
{"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3630
{"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3631
{"vnot", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VBA}},
arch/powerpc/xmon/ppc-opc.c
3632
{"vnor", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3633
{"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3637
{"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3638
{"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3639
{"vcipher", VX (4,1288), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3640
{"vcipherlast", VX (4,1289), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3641
{"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3642
{"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3644
{"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3645
{"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3646
{"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3649
{"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3650
{"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3651
{"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3652
{"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3653
{"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3654
{"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3655
{"vsubcuq", VX (4,1344), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3656
{"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3657
{"bcdutrunc.", VX (4,1345), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3658
{"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3659
{"vavgsh", VX (4,1346), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3660
{"vorc", VX (4,1348), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3664
{"vncipher", VX (4,1352), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3665
{"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3666
{"vncipherlast",VX (4,1353), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3667
{"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3668
{"vbpermq", VX (4,1356), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3669
{"vpksdus", VX (4,1358), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3670
{"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3672
{"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3674
{"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3675
{"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3678
{"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3679
{"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3680
{"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3688
{"vavgsw", VX (4,1410), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3689
{"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3690
{"vnand", VX (4,1412), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3691
{"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3692
{"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3696
{"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3697
{"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3698
{"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3699
{"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3700
{"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3701
{"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3702
{"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3705
{"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3706
{"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3707
{"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3708
{"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3709
{"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3710
{"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3711
{"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3713
{"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3714
{"vsld", VX (4,1476), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3719
{"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3720
{"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3721
{"vbpermd", VX (4,1484), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3722
{"vpksdss", VX (4,1486), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3723
{"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3725
{"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3727
{"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3728
{"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3731
{"vsububs", VX (4,1536), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3752
{"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3753
{"vextublx", VX (4,1549), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
arch/powerpc/xmon/ppc-opc.c
3754
{"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3757
{"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3760
{"vextuhlx", VX (4,1613), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
arch/powerpc/xmon/ppc-opc.c
3762
{"vsubuws", VX (4,1664), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3763
{"vshasigmaw", VX (4,1666), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
arch/powerpc/xmon/ppc-opc.c
3764
{"veqv", VX (4,1668), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3768
{"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3769
{"vmrgow", VX (4,1676), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3770
{"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
arch/powerpc/xmon/ppc-opc.c
3771
{"vshasigmad", VX (4,1730), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
arch/powerpc/xmon/ppc-opc.c
3772
{"vsrd", VX (4,1732), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3778
{"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3781
{"vsrv", VX (4,1796), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3785
{"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3786
{"vextubrx", VX (4,1805), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
arch/powerpc/xmon/ppc-opc.c
3789
{"vsubshs", VX (4,1856), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3792
{"vslv", VX (4,1860), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3794
{"vextuhrx", VX (4,1869), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
arch/powerpc/xmon/ppc-opc.c
3801
{"vsubsws", VX (4,1920), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3807
{"vsumsws", VX (4,1928), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3808
{"vmrgew", VX (4,1932), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
arch/powerpc/xmon/ppc-opc.c
3809
{"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},