drivers/gpu/drm/xe/abi/guc_relay_actions_abi.h

168

(VF2PF_QUERY_RUNTIME_RESPONSE_MSG_MIN_LEN + VF2PF_QUERY_RUNTIME_MAX_COUNT * 2)

drivers/gpu/drm/xe/abi/guc_relay_actions_abi.h

172

((GUC_RELAY_MSG_MAX_LEN - VF2PF_QUERY_RUNTIME_RESPONSE_MSG_MIN_LEN) / 2)

drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c

335

if (unlikely(resp_size < VF2PF_QUERY_RUNTIME_RESPONSE_MSG_MIN_LEN))

drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c

342

max_chunks = (resp_size - VF2PF_QUERY_RUNTIME_RESPONSE_MSG_MIN_LEN) / chunk_size;

drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c

344

reg_data_buf = (void *)(response + VF2PF_QUERY_RUNTIME_RESPONSE_MSG_MIN_LEN);

drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c

355

return VF2PF_QUERY_RUNTIME_RESPONSE_MSG_MIN_LEN + ret * hxg_sizeof(struct reg_data);

drivers/gpu/drm/xe/xe_gt_sriov_vf.c

1002

reg->offset = response[VF2PF_QUERY_RUNTIME_RESPONSE_MSG_MIN_LEN + 2 * i];

drivers/gpu/drm/xe/xe_gt_sriov_vf.c

1003

reg->value = response[VF2PF_QUERY_RUNTIME_RESPONSE_MSG_MIN_LEN + 2 * i + 1];

drivers/gpu/drm/xe/xe_gt_sriov_vf.c

942

u32 response[VF2PF_QUERY_RUNTIME_RESPONSE_MSG_MIN_LEN + 32]; /* up to 16 regs */

drivers/gpu/drm/xe/xe_gt_sriov_vf.c

943

u32 limit = (ARRAY_SIZE(response) - VF2PF_QUERY_RUNTIME_RESPONSE_MSG_MIN_LEN) / 2;

drivers/gpu/drm/xe/xe_gt_sriov_vf.c

969

if (unlikely(ret < VF2PF_QUERY_RUNTIME_RESPONSE_MSG_MIN_LEN)) {

drivers/gpu/drm/xe/xe_gt_sriov_vf.c

973

if (unlikely((ret - VF2PF_QUERY_RUNTIME_RESPONSE_MSG_MIN_LEN) % 2)) {

drivers/gpu/drm/xe/xe_gt_sriov_vf.c

978

num = (ret - VF2PF_QUERY_RUNTIME_RESPONSE_MSG_MIN_LEN) / 2;