AC_VERB_SET_POWER_STATE
{0x01, AC_VERB_SET_POWER_STATE, 0x03},
AC_VERB_SET_POWER_STATE, 0x03);
{0x01, AC_VERB_SET_POWER_STATE, 0x00}, /* AFG: D0 */
{0x01, AC_VERB_SET_POWER_STATE, 0x00}, /* AFG: D0 */
{0x07, AC_VERB_SET_POWER_STATE, 0x00}, /* S/PDIF Rx: D0 */
{0x08, AC_VERB_SET_POWER_STATE, 0x00}, /* S/PDIF Tx: D0 */
AC_VERB_SET_POWER_STATE, AC_PWRST_D3);
AC_VERB_SET_POWER_STATE, AC_PWRST_D3);
AC_VERB_SET_POWER_STATE, state);
snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
AC_VERB_SET_POWER_STATE, AC_PWRST_D3);
AC_VERB_SET_POWER_STATE,
snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
AC_VERB_SET_POWER_STATE,
AC_VERB_SET_POWER_STATE, target);
if (verb != AC_VERB_SET_POWER_STATE) {
snd_hdac_codec_read(hdev, hdev->afg, 0, AC_VERB_SET_POWER_STATE,
snd_hdac_codec_read(hdev, hdev->afg, 0, AC_VERB_SET_POWER_STATE,
AC_VERB_SET_POWER_STATE,
#define RT274_SET_POWER(NID) VERB_CMD(AC_VERB_SET_POWER_STATE, NID, 0)
#define RT286_SET_POWER(NID) VERB_CMD(AC_VERB_SET_POWER_STATE, NID, 0)
#define RT298_SET_POWER(NID) VERB_CMD(AC_VERB_SET_POWER_STATE, NID, 0)
HDA_VERB_CMD(AC_VERB_SET_POWER_STATE,