VCLK_POST_DIV
P = aty_postdividers[((pll_regs[VCLK_POST_DIV] >> ((clock_cntl & 3) << 1)) & 3) |
tmp = aty_ld_pll_ct(VCLK_POST_DIV, par);
aty_st_pll_ct(VCLK_POST_DIV, tmp, par);
pll->ct.vclk_post_div = (aty_ld_pll_ct(VCLK_POST_DIV, par) >> tmp) & 0x03U;