VIC_INT_ENABLE
writel(vic->int_enable, base + VIC_INT_ENABLE);
vic->int_enable = readl(base + VIC_INT_ENABLE);
writel(vic->resume_irqs, base + VIC_INT_ENABLE);
writel(1 << irq, base + VIC_INT_ENABLE);
writel(0, base + VIC_INT_ENABLE);